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a blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin ? embedded processor adsp-bf534/adsp-bf536/adsp-bf537 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features up to 600 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring 0.8v to 1.2v core v dd with on-chip voltage regulation 2.5 v and 3.3 v-tolerant i/o with specific 5 v-tolerant pins 182-ball and 208-ball mbga packages memory up to 132k bytes of on-c hip memory comprised of: instruction sram/cache; instruction sram; data sram/cache; additional dedicated data sram; scratchpad sram (see table 1 on page 3 for available memory configurations) external memory controller wi th glueless support for sdram and asynchronous 8-bit and 16-bit memories flexible booting options from external flash, spi and twi memory or from spi, twi, and uart host devices memory management unit providing memory protection peripherals ieee 802.3-compliant 10/100 ethernet mac (adsp-bf536 and adsp-bf537 only) controller area network (can) 2.0b interface parallel peripheral interface (ppi), supporting itu-r 656 video data formats two dual-channel, full-duple x synchronous serial ports (sports), supporting eight stereo i 2 s channels 12 peripheral dmas, 2 mastered by the ethernet mac two memory-to-memory dmas with external request lines event handler with 32 interrupt inputs serial peripheral interface (spi)-compatible two uarts with irda ? support two-wire interface (twi) controller eight 32-bit timer/counte rs with pwm support real-time clock (rtc) and watchdog timer 32-bit core timer 48 general-purpose i/os (gpios), 8 with high current drivers on-chip pll capable of 1 to 63 frequency multiplication debug/jtag interface figure 1. function al block diagram ethernet mac (adsp-bf536/ bf537 only) timers 0-7 uart 0-1 ppi sport1 spi watchdog timer rtc twi can sport0 gpio port f gpio port h gpio port g port j external port flash, sdram control boot rom jtag test and emulation voltage regulator dma controller l1 instruction memory l1 data memory b interrupt controller peripheral access bus d m a a c c e s s b u s external access bus dma core bus d m a e x t e r n a l b u s p e r i p h e r a l a c c e s s b u s 16
rev. b | page 2 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 table of contents general description ................................................. 3 portable low power architecture ............................. 3 system integration ................................................ 3 blackfin processor peripherals ................................. 3 blackfin processor core .......................................... 4 memory architecture ............................................ 5 dma controllers .................................................. 8 real-time clock ................................................... 9 watchdog timer .................................................. 9 timers ............................................................... 9 serial ports (sports) .......................................... 10 serial peripheral interface (spi) port ....................... 10 uart ports ...................................................... 10 controller area network (can) ............................ 11 twi controller interface ...................................... 11 10/100 ethernet mac .......................................... 11 ports ................................................................ 12 parallel peripheral interface (ppi) ........................... 12 dynamic power management ................................ 13 voltage regulation .............................................. 14 clock signals ..................................................... 14 booting modes ................................................... 16 instruction set description ................................... 16 development tools ............................................. 17 designing an emulator-compatible processor board .. 18 related documents ............................................. 18 pin descriptions .................................................... 19 specifications ........................................................ 23 operating conditions .......................................... 23 electrical characteristics ....................................... 24 absolute maximum ratings .................................. 25 esd sensitivity ................................................... 25 package information ............................................ 25 timing specifications ........................................... 26 asynchronous memory read cycle timing ............ 28 asynchronous memory write cycle timing ........... 29 external port bus request and grant cycle timing .. 30 sdram interface timing .................................. 31 external dma request timing ............................ 32 parallel peripheral interface timing ...................... 33 serial ports ..................................................... 36 serial peripheral interface portmaster timing ...... 40 serial peripheral interface portslave timing ........ 41 universal asynchronous rece iver-transmitter (uart) portsreceive and transmit timing ................. 42 general-purpose port timing ............................. 43 timer cycle timing .......................................... 44 timer clock timing ......................................... 45 jtag test and emulation port timing .................. 46 10/100 ethernet mac controller timing ............... 47 output drive currents ......................................... 50 power dissipation ............................................... 53 test conditions .................................................. 54 capacitive loading .............................................. 55 thermal characteristics ........................................ 58 182-ball mini-bga pinout ....................................... 59 208-ball sparse mi ni-bga pinout .............................. 62 outline dimensions ................................................ 65 surface mount design .......................................... 66 ordering guide ..................................................... 66 revision history 7/07revision b for this revision of the da ta sheet, the adsp-bf534, adsp-bf536, and adsp-bf537 ha ve been combined into a single family data sheet. because of this change, not all processor features and attributes apply across all products. see table 1 on page 3 for a breakdown of product offerings. added table 10, maximum duty cycle for input transient voltage ............................................................. 25 added universal asynchronous re ceiver-transmitter (uart) portsreceive and transmit timing ......................... 42 revised figure 47 , figure 48 , and figure 49 under test conditions ..................................................... 54 added 208-ball mini bga thermal characteristics on page 58 and 208-ball sparse mini-bga pinout on page 62 .
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 3 of 68 | july 2006 general description the adsp-bf534/adsp-bf536/ad sp-bf537 processors are members of the blackfin family of products, incorporating the analog devices/intel micro si gnal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantages of a clean, orthogonal risc- like microprocessor instructio n set, and single-instruction, multiple-data (simd) multimedia capabilities into a single instruction-set architecture. the adsp-bf534/adsp-bf536/ad sp-bf537 processors are completely code and pin compat ible. they differ only with respect to their performance, on -chip memory, and presence of the ethernet mac module. specif ic performance, memory, and feature configurations are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, the blackfin processo rs are the platform of choice for next-generation applications that require risc-like pro- grammability, multimedia suppo rt, and leading-edge signal processing in one integrated package. portable low power architecture blackfin processors provide world-class power management and performance. they are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of oper ation to significantl y lower overall power consumption. this capability can result in a substantial reduc- tion in power consum ption, compared with just varying the frequency of operation. this a llows longer battery life for portable appliances. system integration the blackfin processor is a highly integrated system-on-a-chip solution for the next generati on of embedded network-con- nected applications. by combining industry-standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, without the need for costly external components. the system peripherals include an ieee-compliant 802.3 10/100 ethernet mac (adsp-bf536 and adsp-bf537 only), a can 2.0b controller, a twi controller, two uart ports, an spi port, tw o serial ports (sports), nine general-purpose 32-bit timers (eight with pwm capability), a real-time clock, a watchdog timer, and a parallel peripheral interface (ppi). blackfin processor peripherals the adsp-bf534/adsp-bf536/a dsp-bf537 processors con- tains a rich set of peripherals co nnected to the core via several high bandwidth buses, providing flexibility in system configura- tion as well as excellent overall system performance (see the block diagram on page 1 ). the processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt cont roller for flexib le management of interrupts from the on-chip pe ripherals or external sources, and power management control functions to tailor the perfor- mance and power characteristics of the processor and system to many application scenarios. all of the peripherals, except for the general-purpose i/o, can, twi, real-time clock, and timers, are supported by a flexible dma structure. there are also separate memory dma channels dedicated to data transfers be tween the processors various memory spaces, including external sdram and asynchronous memory. multiple on-chip buse s running at up to 133 mhz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. the blackfin processors include an on-chip voltage regulator in support of the processors dyna mic power management capabil- ity. the voltage regulator provides a range of core voltage levels when supplied from a single 2. 25 v to 3.6 v inpu t. the voltage regulator can be bypassed at the users discretion. table 1. processor comparison features adsp-bf534 adsp-bf536 adsp-bf537 ethernet mac 1 1 can 1 1 1 twi 1 1 1 sports 2 2 2 uarts 2 2 2 spi 1 1 1 gp timers 8 8 8 watchdog timers 1 1 1 rtc 1 1 1 parallel peripheral interface 1 1 1 gpios 48 48 48 memory configuration l1 instruction sram/cache 16k bytes 16k bytes 16k bytes l1 instruction sram 48k bytes 48k bytes 48k bytes l1 data sram/cache 32k bytes 32k bytes 32k bytes l1 data sram 32k bytes 32k bytes l1 scratchpad 4k b ytes 4k bytes 4k bytes l3 boot rom 2k byte s 2k bytes 2k bytes maximum speed grade 500 mhz 400 mhz 600 mhz package options: sparse mini-bga mini-bga 208-ball 182-ball 208-ball 182-ball 208-ball 182-ball
rev. b | page 4 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 blackfin processor core as shown in figure 2 on page 4 , the blackfin processor core contains two 16-bit mu ltipliers, two 40-bit accumulators, two 40-bit alus, four video alus, an d a 40-bit shifter. the compu- tation units process 8-, 16-, or 32- bit data from the register file. the compute register file contains eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compar e/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). if the second alu is used, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.h r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 5 of 68 | july 2006 the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram and cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and co re resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the adsp-bf534/adsp-bf536/ad sp-bf537 processors view memory as a single unified 4g byte address space, using 32-bit addresses. all resources, includ ing internal memory, external memory, and i/o control registers, occupy separate sections of this common address space. th e memory portions of this address space are arranged in a hi erarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or sram, and larger, lower cost, and performance off-chip memory systems. see figure 3 . the on-chip l1 memory system is the highest performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion wi th sdram, flash memory, and sram, optionally accessing up to 516m bytes of physical memory. the memory dma controller prov ides high bandwidth data- movement capability. it can perform block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the adsp-bf534/adsp-bf536/a dsp-bf537 processors have three blocks of on-chip memory providing high-bandwidth access to the core. the first block is the l1 instruction memory, consisting of 64k bytes sram, of which 16k bytes can be configured as a four-way set-associative cache. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of up to two banks of up to 32k bytes each. each memory bank is configurable, offering both cache and sram functional- ity. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram, which runs at the same speed as the l1 memories, but is only accessible as data sram, and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the ebiu. this 16-bit interface provides a glueless connection to a bank of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. the pc133-compliant sdram cont roller can be programmed to interface to up to 512m bytes of sdram. a separate row can be open for each sdram internal bank, and the sdram con- troller supports up to 4 inte rnal sdram banks, improving overall performance. the asynchronous memory cont roller can be programmed to control up to four banks of devi ces with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks are only contiguo us if each is fully populated with 1m byte of memory. i/o memory space the adsp-bf534/adsp-bf536/a dsp-bf537 processors do not define a separate i/o sp ace. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control registers mapped into memory-mapped registers (mmrs) at addresses near the to p of the 4g byte address space. these are separated into two sma ller blocks, one which contains the control mmrs for all core functions, and the other which contains the registers needed fo r setup and control of the on- chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on- chip peripherals.
rev. b | page 6 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 booting the blackfin processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. if the blackfin processor is configured to boot from boot rom mem- ory space, the processor starts executing from the on-chip boot rom. for more information, see booting modes on page 16 . event handling the event controller on the blackf in processor handles all asyn- chronous and synchronous even ts to the processor. the blackfin processor provides even t handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneo usly. prioritization ensures that servicing of a higher priority ev ent takes precedence over servic- ing of a lower priority event. the controller provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions C events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to comp lete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return -from-event inst ruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the blackfin processor event cont roller consists of two stages, the core event controller (cec) and the system interrupt con- troller (sic). the core event co ntroller works wi th the system interrupt controller to prioritize and control all system events. figure 3. adsp-bf534/adsp-bf536/adsp-bf537 memory maps reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instructionbankbsram(16kbytes) system mmr registers (2m bytes) reserved reserved data bank b sram/cache (16k bytes) databankbsram(16kbytes) data bank a sram/cache (16k bytes) async memory bank 3 (1m bytes) async memory bank 2 (1m bytes) async memory bank 1 (1m bytes) async memory bank 0 (1m bytes) sdram memory (16m bytes to 512m bytes) instruction sram/cache (16k bytes) i n t e r n a l m e m o r y m a p e x t e r n a l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0xef00 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 databankasram(16kbytes) 0xff90 0000 0xff80 0000 reserved reserved 0xffa0 c000 0xffa0 8000 instructionbankasram(32kbytes) reserved boot rom (2k bytes) 0xef00 0800 adsp-bf534/adsp-bf537 memory map reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instruction bank b sram (16k bytes) system mmr registers (2m bytes) reserved reserved data bank b sram/cache (16k bytes) data bank a sram/cache (16k bytes) async memory bank 3 (1m bytes) async memory bank 2 (1m bytes) async memory bank 1 (1m bytes) async memory bank 0 (1m bytes) sdram memory (16m bytes to 512m bytes) instruction sram/cache (16k bytes) i n t e r n a l m e m o r y m a p e x t e r n a l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0xef00 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 0xff90 0000 0xff80 0000 reserved reserved 0xffa0 c000 0xffa0 8000 instruction bank a sram (32k bytes) reserved reserved reserved boot rom (2k bytes) 0xef00 0800 adsp-bf536 memory map
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 7 of 68 | july 2006 conceptually, interrupts from the peripherals enter into the sic, and are then routed directly into the general-purpose inter- rupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers, leav ing seven prioritized interrupt inputs to support the peripheral s of the blackfin processor. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the processor provides a default mapping, the user can alter the mappings and prioriti es of interrupt events by writ- ing the appropriate values into the interrupt assignment registers (iar). table 3 describes the inputs into the sic and the default mappings into the cec. table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1reset rst 2 nonmaskable interrupt nmi 3exception evx 4reserved 5 hardware error ivhw 6 core timer ivtmr 7 general-purpose interrupt 7 ivg7 8 general-purpose interrupt 8 ivg8 9 general-purpose interrupt 9 ivg9 10 general-purpose interrupt 10 ivg10 11 general-purpose interrupt 11 ivg11 12 general-purpose interrupt 12 ivg12 13 general-purpose interrupt 13 ivg13 14 general-purpose interrupt 14 ivg14 15 general-purpose interrupt 15 ivg15 table 3. system interrupt controller (sic) peripheral interrupt event default mapping peripheral interrupt id pll wakeup ivg7 0 dma error (generic) ivg7 1 dmar0 block interrupt ivg7 1 dmar1 block interrupt ivg7 1 dmar0 overflow error ivg7 1 dmar1 overflow error ivg7 1 can error ivg7 2 ethernet error (adsp-bf536 and adsp-bf537 only) ivg7 2 sport 0 error ivg7 2 sport 1 error ivg7 2 ppi error ivg7 2 spi error ivg7 2 uart0 error ivg7 2 uart1 error ivg7 2 real-time clock ivg8 3 dma channel 0 (ppi) ivg8 4 dma channel 3 (sport 0 rx) ivg9 5 dma channel 4 (sport 0 tx) ivg9 6 dma channel 5 (sport 1 rx) ivg9 7 dma channel 6 (sport 1 tx) ivg9 8 twi ivg10 9 dma channel 7 (spi) ivg10 10 dma channel 8 (uart0 rx) ivg10 11 dma channel 9 (uart0 tx) ivg10 12 dma channel 10 (uart1 rx) ivg10 13 dma channel 11 (uart1 tx) ivg10 14 can rx ivg11 15 can tx ivg11 16 dma channel 1 (ethernet rx, adsp-bf536 and adsp-bf537 only) ivg11 17 port h interrupt a ivg11 17 dma channel 2 (ethernet tx, adsp-bf536 and adsp-bf537 only) ivg11 18 port h interrupt b ivg11 18 timer 0 ivg12 19 timer 1 ivg12 20 timer 2 ivg12 21 timer 3 ivg12 22 timer 4 ivg12 23 timer 5 ivg12 24 timer 6 ivg12 25 timer 7 ivg12 26 port f, g interrupt a ivg12 27 port g interrupt b ivg12 28
rev. b | page 8 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 event control the blackfin processor provides a very flexible mechanism to control the processing of events. in the cec, three registers are used to coordinate and control events. each register is 16 bits wide: ? cec interrupt latch register (ilat) C indicates when events have been latched. th e appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. this register is updated automatically by the controller, but it may be writ- ten only when its corresponding imask bit is cleared. ? cec interrupt mask regist er (imask) C controls the masking and unmasking of indivi dual events. when a bit is set in the imask register, that event is unmasked and is processed by the cec when a sserted. a cleared bit in the imask register masks the event, preventing the processor from servicing the event even though the event may be latched in the ilat register. th is register ma y be read or written while in supervisor mode. (note that general-pur- pose interrupts can be globa lly enabled and disabled with the sti and cli instructions, respectively.) ? cec interrupt pending regi ster (ipend) C the ipend register keeps track of all nested events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but may be read while in supervisor mode. the sic allows further control of event processing by providing three 32-bit interrupt control and status registers. each register contains a bit corresponding to each of the peripheral interrupt events shown in table 3 on page 7 . ? sic interrupt mask register (sic_imask) C controls the masking and unmasking of each peripheral interrupt event. when a bit is set in the regist er, that peripheral event is unmasked and is processed by the system when asserted. a cleared bit in the register masks the peripheral event, pre- venting the processor from servicing the event. ? sic interrupt status regist er (sic_isr) C as multiple peripherals can be ma pped to a single event, this register allows the software to dete rmine which peripheral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wakeup enable register (sic_iwr) C by enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. ( for more infor- mation, see dynamic power management on page 13. ) because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec recognizes and queues the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend output asserted is three core clock cycles; however, the latenc y can be much higher, depend- ing on the activity within and the state of the processor. dma controllers the blackfin processors have multiple, independent dma con- trollers that support automate d data transfers with minimal overhead for the processor co re. dma transfers can occur between the processors internal memories and any of its dma- capable peripherals. additionally, dma transfers can be accom- plished between any of the dma-capable peripherals and external devices connected to th e external memory interfaces, including the sdram controller and the asynchronous mem- ory controller. dma-capable peri pherals include the ethernet mac (adsp-bf536 and adsp-bf537 only), sports, spi port, uarts, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the dma controller supports both one-dimensional (1-d) and two-dimensional (2-d) dma tran sfers. dma transfer initial- ization can be implemented from registers or from sets of parameters called descriptor blocks. the 2-d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types suppo rted by the dma controller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a li nked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address with in a common page. dma channels 12 and 13 (memory dma stream 0) ivg13 29 dma channels 14 and 15 (memory dma stream 1) ivg13 30 software watchdog timer ivg13 31 port f interrupt b ivg13 31 table 3. system interrupt controller (sic) (continued) peripheral interrupt event default mapping peripheral interrupt id
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 9 of 68 | july 2006 in addition to the dedicated peripheral dma channels, there are two memory dma channels provid ed for transfers between the various memories of the proce ssor system. this enables trans- fers of blocks of data betwee n any of the memoriesincluding external sdram, rom, sram, and flash memorywith mini- mal processor intervention. me mory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. the adsp-bf534/adsp-bf536/ad sp-bf537 processors also have an external dma controller capability via dual external dma request pins when used in conjunction with the external bus interface unit (ebiu). this fu nctionality can be used when a high speed interface is required for external fifos and high bandwidth communications periph erals such as usb 2.0. it allows control of the number of data transfers for memdma. the number of transfers per edge is programmable. this feature can be programmed to allow memdma to have an increased priority on the external bus relative to the core. real-time clock the real-time clock (rtc) provides a robust set of digital watch features, including current time, stopwatch, and alarm. the rtc is clocked by a 32.768 kh z crystal external to the processor. the rtc peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a lo w-power state. the rtc provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on pro- grammable stopwatch countdown, or interrupt at a programmed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day, while the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value, with one-second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the processor from sleep mode upon generati on of any rtc wakeup event. additionally, an rtc wakeup ev ent can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from the hibernate operating mode. connect rtc pins rtxi and rtxo with external components as shown in figure 4 . watchdog timer the adsp-bf534/adsp-bf536/adsp-bf537 processors include a 32-bit timer that can be used to implement a software watchdog function. a software watchdog can improve system availability by forcing the proc essor to a known state through generation of a hardware reset, nonmaskable interrupt (nmi), or general-purpose interrupt, if the timer expires before being reset by software. the programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software mu st reload the counter before it counts to zero from the progra mmed value. this protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hard ware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine if the wa tchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the syst em clock (sclk), at a maximum frequency of f sclk . timers there are nine general-purpose programmable timer units in the processor. eight timers have an external pin that can be con- figured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and peri ods of external events. these timers can be synchronized to an external clock input to the sev- eral other associated pf pins, to an external clock input to the ppi_clk input pin, or to the internal sclk. the timer units can be used in conjunction with the two uarts and the can controller to measur e the width of the pulses in the data stream to provide a soft ware auto-baud detect function for the respective serial channels. the timers can generate interrupt s to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. in addition to the eight genera l-purpose progra mmable timers, a ninth timer is also provided. th is extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generating periodic in terrupts in an operating system. figure 4. external components for rtc rtxo c1 c2 x1 suggested components: ecliptek ec38j (through-hole package) epson mc405 12pf load (surface mount package) c1 = 22pf c2 = 22pf r1 = 10m ystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3pf. rtxi r1
rev. b | page 10 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 serial ports (sports) the adsp-bf534/adsp-bf536/ adsp-bf537 processors incorporate two dual-channel synchronous serial ports (sport0 and sport1) for seri al and multiprocessor commu- nications. the sports support the following features: ?i 2 s capable operation. ? bidirectional operation C each sport has two sets of inde- pendent transmit and receive pi ns, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports C each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking C each transmit and re ceive port can either use an external serial clock or generate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 to 32 bits in length, transferred most significant bit first or least significant bit first. ? framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. ? interrupts C each transmit a nd receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through dma. ? multichannel capability C each sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) port the adsp-bf534/adsp-bf536/ad sp-bf537 processors have an spi-compatible port that en ables the processor to communi- cate with multiple spi-compatible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosi, and master input- slave output, miso) and a clock pin (serial clock, sck). an spi chip select input pin (spiss ) lets other spi devices select the processor, and seven spi chip select output pins (spisel7C1 ) let the processor select other spi de vices. the spi select pins are reconfigured programmable flag pins. using these pins, the spi port provides a full-duplex, sync hronous serial interface, which supports both master/slave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has an integrated dma controller, configurable to support transmit or receive data streams. the spis dma controller can only serv ice unidirectional accesses at any given time. the spi ports clock rate is calculated as: where the 16-bit spi_baud register contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart ports the adsp-bf534/adsp-bf536/a dsp-bf537 processors pro- vide two full-duplex universal asynchronous receiver and transmitter (uart) ports, which are fully compatible with pc- standard uarts. each uart port provides a simplified uart interface to other peripherals or hosts, supporting full-duplex, dma-supported, asynchronous tr ansfers of serial data. a uart port includes support for five to eight data bits, one or two stop bits, and none, even, or odd parity. each uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. each uart ports baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk /16) bits per second. ? supporting data formats from 7 to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as: where the 16-bit uartx_divisor comes from the dlh register (most significant 8 bits) and uart x_dll register (least signifi- cant 8 bits). spi clock rate f sclk 2 spi_baud -------------------------------- = uart clock rate f sclk 16 uart_divisor ----------------------------------------------- =
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 11 of 68 | july 2006 in conjunction with the general-purpose timer functions, auto- baud detection is supported. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda) serial infrared physical layer link specification (sir) protocol. controller area network (can) the adsp-bf534/adsp-bf536/ad sp-bf537 processors offer a can controller that is a communication controller imple- menting the can 2.0b (active) protocol. this protocol is an asynchronous communications protocol used in both industrial and automotive control systems. the can protocol is well- suited for control applications du e to its capability to communi- cate reliably over a network, since the protocol incorporates crc checking message error tracking, and fault node confinement. the can controller offers the following features: ? 32 mailboxes (eight receive only, eight transmit only, 16 configurable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29-bit) identifier (id) message formats. ? support for remote frames. ? active or passive network support. ? can wakeup from hibernation mode (lowest static power consumption mode). ? interrupts, including: tx complete, rx complete, error, global. the electrical characteristics of each network connection are very demanding so the can interface is typically divided into two parts: a controller and a tran sceiver. this allows a single controller to support different drivers and can networks. the can module represents only the co ntroller part of the interface. the controller interface supports connection to 3.3 v high- speed, fault-tolerant, single-wire transceivers. twi controller interface the adsp-bf534/adsp-bf536/adsp-bf537 processors include a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi is compatible with the widely used i 2 c ? bus standard. the twi module offers the capabiliti es of simultaneous master and slave operation, support for both 7-bit addressing and multime- dia data arbitration. the twi interface utilizes two pins for transferring clock (scl) and data (sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compatible with 5 v logic levels. additionally, the processors tw i module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. 10/100 ethernet mac the adsp-bf536 and adsp-bf537 processors offer the capa- bility to directly connect to a network by way of an embedded fast ethernet media access co ntroller (mac) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 ethernet ma c peripheral is fully compli- ant to the ieee 802.3-2002 st andard, and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. some standard features are: ? support of mii and rmii protocols for external phys. ? full duplex and half duplex modes. ? data framing and encapsulation: generation and detection of preamble, length padding, and fcs. ? media access management (in half-duplex operation): col- lision and contention handling, including control of retransmission of collision fr ames and of back-off timing. ? flow control (in full-duplex operation): generation and detection of pause frames. ? station management: generation of mdc/mdio frames for read-write access to phy registers. ? sclk operating range down to 25 mhz (active and sleep operating modes). ? internal loopback from tx to rx. some advanced features are: ? buffered crystal output to external phy for support of a single crystal system. ? automatic checksum computat ion of ip header and ip payload fields of rx frames. ? independent 32-bit descriptor-driven rx and tx dma channels. ? frame status delivery to memory via dma, including frame completion semaphores , for efficient buffer queue management in software. ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations. ? convenient frame alignment modes support even 32-bit alignment of encapsulated rx or tx ip packet data in mem- ory after the 14-byte mac header. ? programmable ethernet event interrupt supports any com- bination of: ? any selected rx or tx frame status conditions. ? phy interrupt condition. ? wakeup frame detected. ? any selected mac management counter(s) at half-full. ? dma descriptor error. ? 47 mac management statistics counters with selectable clear-on-read behavior and pr ogrammable interrupts on half maximum value.
rev. b | page 12 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 ? programmable rx address fi lters, including a 64-bit address hash table for multicast and/or unicast frames, and programmable filter modes fo r broadcast, multicast, uni- cast, control, and damaged frames. ? advanced power management supporting unattended transfer of rx and tx frames and status to/from external memory via dma during low-power sleep mode. ? system wakeup from sleep operating mode upon magic packet or any of four user-d efinable wakeup frame filters. ? support for 802.3q tagged vlan frames. ?programmable mdc clock rate and preamble suppression. ? in rmii operation, 7 unused pins may be configured as gpio pins for other purposes. ports the adsp-bf534/adsp-bf536/ adsp-bf537 processors group the many peripheral signals to four portsport f, port g, port h, and port j. most of th e associated pins are shared by multiple signals. the ports func tion as multiplexer controls. eight of the pins (port f7C0) offer high source/high sink current capabilities. general-purpose i/o (gpio) the processors have 48 bidirectional, general-purpose i/o (gpio) pins allocated across three separate gpio modules portfio, portgio, and porthio, associated with port f, port g, and port h, respectively. port j does not provide gpio functionality. each gpio-capable pin shares functionality with other processor peripherals via a multiplexing scheme; however, the gpio functionality is the default state of the device upon power-up. neither gpio output or input drivers are active by default. each general-purpose port pin can be individually con- trolled by manipulation of the po rt control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status registers C the processors employ a write one to modify mechanism that allows any combi- nation of individual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. four control registers ar e provided. one register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. reading the gpio status register allows software to interrogate the sense of the pins. ? gpio interrupt mask register s C the two gpio interrupt mask registers allow each indi vidual gpio pin to function as an interrupt to the processor. similar to the two gpio control registers that are used to set and clear individual pin values, one gpio interrupt mask register sets bits to enable interrupt function, and the other gpio interrupt mask register clears bits to disable interrupt function. gpio pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C the two gpio inter- rupt sensitivity registers specif y whether individual pins are level- or edge-sensitive and specifyif edge-sensitive whether just the rising edge or both the rising and falling edges of the signal are signific ant. one register selects the type of sensitivity, and one re gister selects which edges are significant for edge-sensitivity. parallel peripheral interface (ppi) the adsp-bf534/adsp-bf536/a dsp-bf537 processors pro- vide a parallel peripheral inte rface (ppi) that can connect directly to paralle l a/d and d/a converters, itu-r-601/656 video encoders and decoders, and other general-purpose peripherals. the ppi consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. in itu-r-656 modes, the ppi receiv es and parses a data stream of 8-bit or 10-bit data elements . on-chip decode of embedded preamble control and synchronization information is supported. three distinct itu-r- 656 modes are supported: ? active video only mode C the ppi does not read in any data between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during the vertical blanking intervals. in this mode, the control byte sequences are not stored to memory; they are filtered by the ppi. ? vertical blanking only mode C the ppi only transfers verti- cal blanking interval (vbi) data, as well as horizontal blanking information and control byte sequences on vbi lines. ? entire field mode C the entire incoming bitstream is read in through the ppi. this includes active video, control pre- amble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. though not explicitly supported, itu-r-656 output functional- ity can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data ou t the ppi in a frame sync-less mode. the processors 2-d dma feat ures facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. the general-purpose modes of the ppi are intended to suit a wide variety of data capture and transmission applications. the modes are divided into four main categories, each allowing up to 16 bits of data tran sfer per ppi_clk cycle: ? data receive with internally generated frame syncs ? data receive with externally generated frame syncs ? data transmit with internally generated frame syncs ? data transmit with externally generated frame syncs
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 13 of 68 | july 2006 these modes support adc/dac connections, as well as video communication with hardware signalling. many of the modes support more than one level of frame synchronization. if desired, a programmable delay can be inserted between asser- tion of a frame sync and reception/transmission of data. dynamic power management the adsp-bf534/adsp-bf536/ad sp-bf537 processors pro- vide five operating modes, each with a different performance and power profile. in addition, dynamic power management provides the control functions to dynamically alter the proces- sor core supply voltage, furt her reducing power dissipation. control of clocking to each of the peripherals also reduces power consumption. see table 4 for a summary of the power settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. in this mode, the clkin to cclk multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. dma access is available to appropriately configured l1 memories. in the active mode, it is possible to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before transitioning to the full-on or sleep modes. sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally an external event or rtc ac tivity wakes up the processor. when in the sleep mo de, asserting wakeup causes the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled, the processor transitions to the full on mode. if bypass is enabled, the processor transi- tions to the active mode. system dma access to l1 me mory is not supported in sleep mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the proc essor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals, such as the rtc, may still be ru nning but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode, an rtc asynchronous interrupt causes the proces- sor to transition to the active mode. assertion of reset while in deep sleep mode causes the pr ocessor to transi tion to the full- on mode. hibernate operating modemaximum static power savings the hibernate mode maximizes static power savings by dis- abling the voltage and clocks to the processor core (cclk) and to all of the synchronous periph erals (sclk). the internal volt- age regulator for the processor can be shut off by writing b#00 to the freq bits of the vr_ctl register. this disables both cclk and sclk. furthermore, it sets the internal power supply volt- age (v ddint ) to 0 v to provide the greatest power savings. to preserve the processor state, prio r to removing power, any criti- cal information stored interna lly (memory contents, register contents, etc.) must be written to a non volatile storage device. since v ddext is still supplied in this mode, all of the external pins three-state, unless otherwise specified. this allows other devices that are connected to the processor to still have power applied without drawing unwanted current. the ethernet or can modules can wake up the internal supply regulator. the regulator can also be woken up by a real-time clock wakeup event or by asserting the reset pin, both of which initiate the hard ware reset sequence. with the exception of the vr_ctl and the rtc registers, all internal registers and memories lose their content in the hiber- nate state. state variables may be held in external sram or sdram. the ckelow bit in the vr_ctl register controls whether sdram operates in self-r efresh mode which allows it to retain its content while the processor is in reset. power savings as shown in table 5 , the processors support three different power domains which maximizes flexibility, while maintaining compliance with industry standa rds and conventions. by isolat- ing the internal logic of the processor into its own power domain, separate from the rt c and other i/o, the processor can take advantage of dynamic power management, without affecting the rtc or other i/o de vices. there are no sequencing requirements for the various power domains. table 4. power settings mode pll pll bypassed core clock (cclk) system clock (sclk) internal power (vddint) full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
rev. b | page 14 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 the dynamic power management feature allows both the pro- cessors input voltage (v ddint ) and clock frequency (f cclk ) to be dynamically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% re sults in a 25% reduction in power dissipation, while reducing the voltage by 25% reduces power dissipation by more than 40%. further, these power savings are additive, in that if the clock frequency and supply voltage are both redu ced, the power savings can be dramatic, as shown in the following equations. the power savings factor is calculated as: where the variables in the equations are: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage t nom is the duration running at f cclknom t red is the duration running at f cclkred the percent power savings is calculated as: voltage regulation the adsp-bf534/adsp-bf536/ adsp-bf537 processor pro- vides an on-chip voltage regulator that can generate processor core voltage levels (0.85 v to 1.2 v guaranteed from C5% to +10%) from an external 2.25 v to 3.6 v supply. figure 5 shows the typical external components required to complete the power management system. the regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (vr_ctl) in in crements of 50 mv. to reduce standby power consumption, the internal voltage regulator can be programmed to re move power to the pr ocessor core while keeping i/o power supplied. while in hibernate mode, v ddext can still be applied, eliminating the need for external buffers. the voltage regulator can be ac tivated from this power-down state by asserting the reset pin, which then initiates a boot sequence. the regulator can also be disabled and bypassed at the users discretion. clock signals the adsp-bf534/adsp-bf536/ad sp-bf537 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the proce ssors include an on-chip oscilla- tor circuit, an external crystal may be used. for fundamental frequency operation, use the circuit shown in figure 6 . a parallel-resonant, fundamenta l frequency, microprocessor- grade crystal is connected across the clkin and xtal pins. the on-chip resistance between clkin and the xtal pin is in the 500 k range. further parallel resi stors are typically not rec- ommended. the two capacitors and the series resistor shown in figure 6 fine-tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 6 are typical values only. the capacitor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufact urer. the user should verify the customized values based on care ful investigations of multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modifi ed to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 6 . a design procedure fo r third-overtone oper- ation is discussed in detail in application note ee-168. the clkbuf pin is an output pin, and is a buffer version of the input clock. this pin is particularly useful in ethernet applica- tions to limit the number of required clock sources in the system. in this type of applic ation, a single 25 mhz or 50 mhz crystal may be applied directly to the processors. the 25 mhz or 50 mhz output of clkbuf can then be connected to an exter- nal ethernet mii or rmii phy device. table 5. power domains power domain v dd range all internal logic, except rtc v ddint rtc internal logic and crystal i/o v ddrtc all other i/o v ddext power savings factor f cclkred f cclknom --------------------- v ddintred v ddintnom -------------------------- ?? ?? 2 t red t nom ------------ - ? ? ? ? = % power savings 1 power savings factor ? () 100% = figure 5. voltage regulator circuit v ddext v ddint vr out 1-0 external components 2.25v to 3.6v input voltage range nds8434 zhcs1000 100f 1f 10h 0.1f note: vr out 1-0 should be tied together externally and designer should minimize trace length to nds8434. 100f
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 15 of 68 | july 2006 because of the default 10x pll multiplier, providing a 50 mhz clkin exceeds the recommended operating conditions of the lower speed grades. because of th is restriction, a 50 mhz rmii phy cannot be clocked directly from the clkbuf pin. either provide a separate 50 mhz clock source, or use an rmii phy with 25 mhz clock input options. the clkbuf output is active by default and can be disabled using the vr_ctl register for power savings. the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 7 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programmable 0.5 to 64 multiplication factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 10 , but it can be modi- fied by a software in struction sequence in the pll_ctl register. on-the-fly cclk and sclk freq uency changes can be effected by simply writing to the pll_d iv register. whereas the maxi- mum allowed cclk and sclk rates depend on the applied voltages v ddint and v ddext , the vco is always permitted to run up to the frequency specified by the parts speed grade. the clkout pin reflects the sclk frequency to the off-chip world. it belongs to the sdram interface, but it functions as reference signal in other timing specificat ions as well. while active by default, it can be disabled using the ebiu_sdgctl and ebiu_amgctl registers. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. the maximum cclk frequency not only depends on the parts speed grade (see ordering guide on page 66 ), it also depends on the applied v ddint voltage. see table 12 and table 13 for details. the maximal system clock rate (sclk) depends on the chip package and the applied v ddext voltage (see table 16 ). figure 6. external crystal connections clkin clkout xtal en clkbuf to pll circuitry for overtone operation only: note: values marked with * must be customized depending on the crystal and layout. please analyze carefully. 18pf* en 18pf* 330 * blackfin figure 7. frequency mo dification methods table 6. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50 table 7. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25 pll 0.5 -64 1to 15 1 , 2, 4, 8 vco clkin ?fine? adjustment requires pll sequencing ?course? adjustment on the fly cclk sclk sclk cclk sclk 1 3 3 mhz
rev. b | page 16 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 booting modes the adsp-bf534/adsp-bf536/a dsp-bf537 processor has six mechanisms (listed in table 8 ) for automatically loading inter- nal and external memory after a reset. a seventh mode is provided to execute from extern al memory, bypassing the boot sequence. the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the following modes: ? execute from 16-bit external memory C execution starts from address 0x2000 0000 with 16-bit packing. the boot rom is bypassed in this mode. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access time s; 4-cycle setup). ? boot from 8-bit and 16-bit external flash memory C the 8-bit or 16-bit flash boot routine located in boot rom memory space is set up usin g asynchronous memory bank 0. all configuration settings ar e set for the slowest device possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). the boot rom evaluates the first byte of the boot stream at address 0x2000 0000. if it is 0x40, 8-bit boot is performed. a 0x60 byte as sumes a 16-bit memory device and performs 8-bit dma. a 0x 20 byte also assumes 16-bit memory but performs 16-bit dma. ? boot from serial spi memory (eeprom or flash) C 8-, 16-, or 24-bit addressable devices are supported as well as at45db041, at45db081, at45db161, at45db321, at45db642, and at45db1282 dataflash ? devices from atmel. the spi uses the pf10/spi ssel1 output pin to select a single spi eeprom/fl ash device, submits a read command and successive address bytes (0x00) until a valid 8-, 16-, or 24-bit, or atmel ad dressable device is detected, and begins clocking data into the processor. ? boot from spi host device C the blackfin processor oper- ates in spi slave mode and is configured to receive the bytes of the .ldr file from an spi host (master) agent. to hold off the host device from transmitting while the boot rom is busy, the blackfin processo r asserts a gpio pin, called host wait (hwait), to signal the host device not to send any more bytes until the flag is deasserted. the flag is cho- sen by the user and this information is transferred to the blackfin processor via bits 10:5 of the flag header. ? boot from uart C using an autobaud handshake sequence, a boot-stream-forma tted program is downloaded by the host. the host agent selects a baud rate within the uarts clocking capabilities. when performing the auto- baud, the uart expects an @ (boot stream) character (8 bits data, 1 start bit, 1 stop bit, no parity bit) on the rxd pin to determine the bit rate. it then replies with an acknowledgement that is composed of 4 bytes: 0xbf, the value of uart_dll, the valu e of uart_dlh, and 0x00. the host can then download the boot stream. when the processor needs to hold off the host, it deasserts cts. therefore, the host must monitor this signal. ? boot from serial twi memory (eeprom/flash) C the blackfin processor operates in master mode and selects the twi slave with the unique id 0xa0. it submits successive read commands to the memory device starting at two byte internal address 0x 0000 and begins clocking data into the processor. the twi memory de vice should comply with philips i 2 c bus specification version 2.1 and have the capa- bility to auto-increment its internal address counter such that the contents of the me mory device can be read sequentially. ? boot from twi host C the twi host agent selects the slave with the unique id 0x5f. th e processor replies with an acknowledgement and the host can then download the boot stream. the twi host agent should comply with philips i 2 c bus specification version 2.1. an i 2 c multi- plexer can be used to select one processor at a time when booting multiple processors from a single twi. for each of the boot modes, a 10-byte header is first brought in from an external device. the he ader specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the start of l1 instruction sram. in addition, bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. for this case, th e processor jumps directly to the beginning of l1 in struction memory. to augment the boot modes, a se condary software loader can be added to provide additional booting mechanisms. this second- ary loader could provide the capability to boot from flash, variable baud rate, and other sour ces. in all boot modes except bypass, program execution starts from on-chip l1 memory address 0xffa0 0000. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the table 8. booting modes bmode2C0 description 000 execute from 16-bit external memory (bypass boot rom) 001 boot from 8-bit or 16-bit memory (eprom/flash) 010 reserved 011 boot from serial sp i memory (eeprom/flash) 100 boot from spi ho st (slave mode) 101 boot from serial twi memory (eeprom/flash) 110 boot from twi host (slave mode) 111 boot from uart host (slave mode)
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 17 of 68 | july 2006 programmer to use many of the processor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mcu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools the blackfin is supported with a complete set of crosscore ? ? software and hardware development tools, including analog devices emulators and the visualdsp++ ? ? development environment. the sa me emulator hardware that supports other analog devices processors also fully emulates the blackfin. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler that is based on an algebraic syntax, an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-leve l simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathemati- cal functions. a key point fo r these tools is c/c++ code efficiency. the comp iler has been deve loped for efficient translation of c/c++ code to blackfin assembly. the blackfin processor has architectural features that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the so ftware developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottleneck s in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information). ? insert breakpoints. ? set conditional breakpoints on registers, memory, and stacks. ? trace instruction execution. ? perform linear or statistical profiling of program execution. ? fill, dump, and graphically plot the contents of memory. ? perform source level debugging. ? create custom debugger windows. the visualdsp++ ide lets programmers define and manage software development. its dialog boxes and property pages let programmers configure and manage all development tools, including color syntax highlighting in the visualdsp++ editor. these capabilities pe rmit programmers to: ? control how the development tools process inputs and generate outputs. ? maintain a one-to-one correspondence with the tools command line switches. the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of embedded, real-time programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. the vdk features include th reads, critical and unscheduled regions, semaphores, events, and device flags. the vdk also supports priority-based, pre-emptive, coop erative, and time-sliced sched- uling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but can also be used with standard command line tools. when the vdk is used, the development environment assists th e developer with many error prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk-based objects, and vi sualizing the system state when debugging an application that uses the vdk. ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc.
rev. b | page 18 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 vcse is analog devices techno logy for creating, using, and reusing software components (independent modules of sub- stantial functionality) to quickly and reliably assemble software applications. components can be downloaded from the web and dropped into the application. component archives can be published from within visualdsp++. vcse supports compo- nent implementation in c/c++ or assembly language. the expert linker can be used to visually manipulate the place- ment of code and data in the embedded system. memory utilization can be viewed in a color-coded graphical form. code and data can be easily moved to different areas of the processor or external memory with the dr ag of the mouse. runtime stack and heap usage can be examined. the expert linker is fully com- patible with existing linker definition file (ldf), allowing the developer to move between the graphical and textual environments. analog devices emulators use th e ieee 1149.1 jtag test access port of the blackfin to monito r and control the target board processor during emulation. th e emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. nonintrusive in-circuit emula- tion is assured by the use of th e processors jtag interfacethe emulator does not affect targ et system load ing or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the blackfin processor family. third party software tools include dsp libraries, real-time operating systems, and block di agram design tools. ez-kit lite? evaluation board for evaluation of adsp-b f534/adsp-bf536/adsp-bf537 processors, use the adsp-bf537 ez-kit lite board available from analog devices. orde r part number adds-bf537- ezlite. the board comes with on -chip emulation capabilities and is equipped to enable soft ware development. multiple daughter cards are available. designing an emulator-compatible processor board the analog devices family of em ulators are tools that every sys- tem developer needs in order to test and debug hardware and software systems. analog devi ces has supplied an ieee 1149.1 jtag test access port (tap) on each jtag processor. the emulator uses the tap to access th e internal features of the pro- cessor, allowing the developer to load code, set breakpoints, observe variables, observe memo ry, and examine registers. the processor must be halted to se nd data and commands, but once an operation has been completed by the emulator, the processor system is set running at fu ll speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see analog devices jtag emul ation technical reference (ee-68) on the analog devices website under www.analog.com/ee-notes . this document is updated regularly to keep pace with improvements to emulator support. related documents the following publications that describe the adsp-bf534/ adsp-bf536/adsp-bf537 processors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf537 blackfin proc essor hardware reference ? adsp-bf53x/adsp-bf56x blackfin processor program- ming reference ? adsp-bf537 blackfin processor anomaly list
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 19 of 68 | july 2006 pin descriptions adsp-bf534/adsp-bf536/adsp-b f537 processors pin defi- nitions are listed in table 9 . in order to maintain maximum function and reduce package size and pin count, some pins have dual, multiplexed functions. in cases where pin function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. pins shown with an aster- isk after their name (*) offer high source/high sink current capabilities. all pins are three-stated during and immediately after reset, with the exception of the exte rnal memory interface and the buffered xtal output pin (clkbuf). on the external memory interface, the control and addre ss lines are driven high during reset unless the br pin is asserted. all i/o pins have their input buffers disabled with the exception of the pins noted in the data sheet that need pull-ups or pull- downs if unused. the sda (serial data) and scl (ser ial clock) pins are open drain and therefore require a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value. table 9. pin descriptions pin name type function driver type 1 pull-up/pull-down memory interface addr19C1 o address bus for async access a data15C0 i/o data bus for async/sync access a abe1C0 /sdqm1C0 o byte enables/data masks for async/sync access a br i bus request this pin should be pulled high when not used bg obus grant a bgh o bus grant hang a asynchronous memory control ams3C0 o bank select a ardy i hardware ready control aoe o output enable a are oread enable a awe owrite enable a synchronous memory control sras o row address strobe a scas o column address strobe a swe owrite enable a scke o clock enable a clkout o clock output b sa10 o a10 pin a sms o bank select a
rev. b | page 20 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 port f: gpio/uart1C0/timer7C0/spi/ external dma request (* = high source/high sink pin) pf0* C gpio/ uart0 tx / dmar0 i/o gpio/ uart0 transmit / dma request 0 c pf1* C gpio/ uart0 rx / dmar1 / taci1 i/o gpio/ uart0 receive / dma request 1 / timer1 alternate input capture c pf2* C gpio/ uart1 tx / tmr7 i/o gpio/ uart1 transmit / timer7 c pf3* C gpio/ uart1 rx / tmr6 / taci6 i/o gpio/ uart1 receive / timer6 / timer6 alternate input capture c pf4* C gpio/ tmr5 / spi ssel6 i/o gpio/ timer5 / spi slave select enable 6 c pf5* C gpio/ tmr4 / spi ssel5 i/o gpio/ timer4 / spi slave select enable 5 c pf6* C gpio/ tmr3 / spi ssel4 i/o gpio/ timer3 / spi slave select enable 4 c pf7* C gpio/ tmr2 / ppi fs3 i/o gpio/ timer2 / ppi frame sync 3 c pf8 C gpio/ tmr1 / ppi fs2 i/o gpio/ timer1 / ppi frame sync 2 c pf9 C gpio/ tmr0 / ppi fs1 i/o gpio/ timer0 / ppi frame sync 1 c pf10 C gpio/ spi ssel1 i/o gpio/ spi slave select enable 1 c pf11 C gpio/ spi mosi i/o gpio/ spi master out slave in c pf12 C gpio/ spi miso i/o gpio/ spi master in slave out c this pin should always be pulled high through a 4.7 k resistor if booting via the spi port pf13 C gpio/ spi sck i/o gpio/ spi clock d pf14 C gpio/ spi ss / taclk0 i/o gpio/ spi slave select / alternate timer0 clock input c pf15 C gpio/ ppi clk / tmrclk i/o gpio/ ppi clock / external timer reference c port g: gpio/ppi/sport1 pg0 C gpio/ ppi d0 i/o gpio/ ppi data 0 c pg1 C gpio/ ppi d1 i/o gpio/ ppi data 1 c pg2 C gpio/ ppi d2 i/o gpio/ ppi data 2 c pg3 C gpio/ ppi d3 i/o gpio/ ppi data 3 c pg4 C gpio/ ppi d4 i/o gpio/ ppi data 4 c pg5 C gpio/ ppi d5 i/o gpio/ ppi data 5 c pg6 C gpio/ ppi d6 i/o gpio/ ppi data 6 c pg7 C gpio/ ppi d7 i/o gpio/ ppi data 7 c pg8 C gpio/ ppi d8 / dr1sec i/o gpio/ ppi data 8 / sport1 receive data secondary c pg9 C gpio/ ppi d9 / dt1sec i/o gpio/ ppi data 9 / sport1 transmit data secondary c pg10 C gpio/ ppi d10 / rsclk1 i/o gpio/ ppi data 10 / sport1 receive serial clock d pg11 C gpio/ ppi d11 / rfs1 i/o gpio/ ppi data 11 / sport1 receive frame sync c pg12 C gpio/ ppi d12 / dr1pri i/o gpio/ ppi data 12 / sport1 receive data primary c pg13 C gpio/ ppi d13 / tsclk1 i/o gpio/ ppi data 13 / sport1 transmit serial clock d pg14 C gpio/ ppi d14 / tfs1 i/o gpio/ ppi data 14 / sport1 transmit frame sync c pg15 C gpio/ ppi d15 / dt1pri i/o gpio/ ppi data 15 / sport1 transmit data primary c table 9. pin descriptions (continued) pin name type function driver type 1 pull-up/pull-down
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 21 of 68 | july 2006 port h: gpio/10/100 ethernet mac (on adsp-bf534, these pins are gpio only) ph0 C gpio/ etxd0 i/o gpio/ ethernet mii or rmii transmit d0 e ph1 C gpio/ etxd1 i/o gpio/ ethernet mii or rmii transmit d1 e ph2 C gpio/ etxd2 i/o gpio/ ethernet mii transmit d2 e ph3 C gpio/ etxd3 i/o gpio/ ethernet mii transmit d3 e ph4 C gpio/ etxen i/o gpio/ ethernet mii or rmii transmit enable e ph5 C gpio/ mii txclk / rmii ref_clk i/o gpio/ ethernet mii transmit clock / rmii reference clock e ph6 C gpio/ mii phyint / rmii mdint i/o gpio/ ethernet mii phy interrupt / rmii management data interrupt e ph7 C gpio/ col i/o gpio/ ethernet collision e ph8 C gpio/ erxd0 i/o gpio/ ethernet mii or rmii receive d0 e ph9 C gpio/ erxd1 i/o gpio/ ethernet mii or rmii receive d1 e ph10 C gpio/ erxd2 i/o gpio/ ethernet mii receive d2 e ph11 C gpio/ erxd3 i/o gpio/ ethernet mii receive d3 e ph12 C gpio/ erxdv / taclk5 i/o gpio/ ethernet mii receive data valid / alternate timer5 input clock e ph13 C gpio/ erxclk / taclk6 i/o gpio/ ethernet mii receive clock / alternate timer6 input clock e ph14 C gpio/ erxer / taclk7 i/o gpio/ ethernet mii or rmii receive error / alternate timer7 input clock e ph15 C gpio/ mii crs / rmii crs_dv i/o gpio/ ethernet mii carrier sense / ethernet rmii carrier sense and receive data valid e port j: sport0/twi/spi select/can pj0 C mdc o ethernet management channe l clock e on adsp-bf534 processors, do not connect pj0, and tie pj1 to ground pj1 C mdio i/o ethernet management channel serial data e on adsp-bf534 processors, do not connect pj0, and tie pj1 to ground pj2 C scl i/o twi serial clock f pj3 C sda i/o twi serial data f pj4 C dr0sec/ canrx / taci0 i sport0 receive data secondary/ can receive / timer0 alternate input capture pj5 C dt0sec/ cantx / spi ssel7 o sport0 transmit data secondary/ can transmit / spi slave select enable 7 c pj6 C rsclk0/ taclk2 i/o sport0 receive serial clock/ alternate timer2 clock input d pj7 C rfs0/ taclk3 i/o sport0 receive frame sync/ alternate timer3 clock input c pj8 C dr0pri/ taclk4 i sport0 receive data primary/ alternate timer4 clock input pj9 C tsclk0/ taclk1 i/o sport0 transmit serial clock/ alternate timer1 clock input d pj10 C tfs0/ spi ssel3 i/o sport0 transmit frame sync/ spi slave select enable 3 c pj11 C dt0pri/ spi ssel2 o sport0 transmit data primary/ spi slave select enable 2 c table 9. pin descriptions (continued) pin name type function driver type 1 pull-up/pull-down
rev. b | page 22 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 real time clock rtxi i rtc crystal input this pin should always be pulled low when not used rtxo o rtc crystal output jtag port tck i jtag clock tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset this pin should be pulled low if the jtag port is not used emu o emulation output c clock clkin i clock/crystal input xtal o crystal output clkbuf o buffered xtal output e e mode controls reset ireset nmi i nonmaskable interrupt this pin should always be pulled high when not used bmode2C0 i boot mode strap 2-0 voltage regulator vrout0 o external fet drive vrout1 o external fet drive supplies v ddext pi/o power supply v ddint p internal power supply (regulated from 2.25 v to 3.6 v) v ddrtc p real time clock power supply gnd g external ground 1 see output drive currents on page 50 for more information about each driver types. table 9. pin descriptions (continued) pin name type function driver type 1 pull-up/pull-down
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 23 of 68 | july 2006 specifications note that component specificat ions are subject to change without notice. operating conditions parameter 1 1 specifications subject to change without notice. min nominal max unit v ddint internal supply voltage 2 2 the voltage regulator can generate v ddint at levels of 0.85 v to 1.2 v with C5% to +10% tolerance. to run the processors at 500 mhz or 600 mhz, v ddint must be in an operating range of 1.2 v to 1.32 v. 0.8 1.26 1.32 v v ddext external supply voltage 2.25 2.5 or 3.3 3.6 v v ddrtc real time clock power supply voltage 2.25 3.6 v v ih high level input voltage 3, 4 , @ v ddext = maximum 3 bidirectional pins (data15C0, pf15C0, pg15C0, ph15C0, tf s0, tclk0, rsclk0, rfs0, mdio) and input pins (br , ardy, dr0pri, dr0sec, rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode2C0) of the adsp -bf534/adsp-bf536/adsp-bf537 ar e 3.3 v-tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 4 parameter value applies to all input and bidi rectional pins except clkin, sda, and scl. 2.0 3.6 v v ihclkin high level input voltage 5 , @ v ddext = maximum 5 parameter value applies to clkin pin only. 2.2 3.6 v v ih5v 5.0 v tolerant pins, high level input voltage 6 , @ v ddext = maximum 6 pins sda, scl, and pj4 are 5.0 v tolera nt (always accept up to 5.5 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 2.0 5.0 v v il low level input voltage 3, 7 , @ v ddext = minimum 7 parameter value applies to all input an d bidirectional pins except sda and scl. C0.3 +0.6 v v il5v 5.0 v tolerant pins, low level input voltage 6 , @ v ddext = minimum C0.3 +0.8 v
rev. b | page 24 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 electrical characteristics parameter description test conditions min max unit v oh (all outputs and i/os except port f, port g, port h) high level output voltage 1 1 applies to output an d bidirectional pins. @ v ddext = 3.3 v 10%, i oh = C0.5 ma @ v ddext = 2.5 v 10%, i oh = C0.5 ma v ddext C 0.5 v ddext C 0.5 v v v oh (port f7C0) @ v ddext = 3.3 v 10%, i oh = C8 ma @ v ddext = 2.5 v 10%, i oh = C6 ma v ddext C 0.5 v ddext C 0.5 v v v oh (port f15C8, port g, port h) i oh = C2 ma v ddext C 0.5 v i oh (max combined for port f7C0) v oh = v ddext C 0.5 v min C64 ma i oh (max total for all port f, port g, and port h pins) v oh = v ddext C 0.5 v min C144 ma v ol (all outputs and i/os except port f, port g, port h) low level output voltage 1 @ v ddext = 3.3 v 10%, i ol = 2.0 ma @ v ddext = 2.5 v 10%, i ol = 2.0 ma 0.4 v v ol (port f7C0) @ v ddext = 3.3 v 10%, i ol = 8 ma @ v ddext = 2.5 v 10%, i ol = 6 ma 0.5 0.5 v v v ol (port f15C8, port g, port h) i ol = 2 ma 0.5 v i ol (max combined for port f7C0) v ol = 0.5 v max 64 ma i ol (max total for all port f, port g, and port h pins) v ol = 0.5 v max 144 ma i ih high level input current 2 2 applies to input pins. @ v ddext =3.6 v, v in = 3.6 v 10 a i ih5v high level input current 3 3 applies to input pin pj4. @ v ddext =3.0 v, v in = 5.5 v 10 a i il low level input current 2 @ v ddext =3.6 v, v in = 0 v 10 a i ihp high level input current jtag 4 4 applies to jtag input pins (tck, tdi, tms, trst) . @ v ddext = 3.6 v, v in = 3.6 v 50.0 a i ozh three-state leakage current 5 5 applies to three-statable pins. @ v ddext = 3.6 v, v in = 3.6 v 10 a i ozh5v three-state leakage current 6 6 applies to bidirectional pins pj2 and pj3. @ v ddext =3.0 v, v in = 5.5 v 10 a i ozl three-state leakage current 5 @ v ddext = 3.6 v, v in = 0 v 10 a c in input capacitance 7, 8 7 applies to all signal pins. 8 guaranteed, but not tested. f in = 1 mhz, t ambient = 25c, v in = 2.5 v 8 pf
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 25 of 68 | july 2006 absolute maximum ratings stresses greater than those list ed below may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions greater than those indicated in the operat ional sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package information the information presented in figure 8 and table 11 provides details about the package branding for the blackfin processors. for a complete listing of product availability, see ordering guide on page 66 . esd sensitivity parameter rating internal (core) supply voltage (v ddint )C0.3 v to +1.4 v external (i/o) supply voltage (v ddext )C0.3 v to +3.8 v input voltage C0.5 v to +3.6 v input voltage 1 1 applies to pins scl, sda, and pj4. for other duty cycles, see table 10 . C0.5 v to +5.5 v output voltage swing C0.5 v to v ddext +0.5 v load capacitance 2 2 for proper sdram controller operation, the maximum load ca pacitance is 50 pf (at 3.3 v) or 30 pf (at 2.5 v) for addr19C1, data15C0, abe1C0/sdqm1C0, clkout, scke, sa10, sras, scas, swe, and sms. 200 pf storage temperature range C65 c to +150 c junction temperature underbias +125 c table 10. maximum duty cycle for input 1 transient voltage 1 applies to all signal pins with the ex ception of clkin, xtal, and vrout1C0. v in min (v) v in max (v) 2 2 only one of the listed options ca n apply to a part icular design. maximum duty cycle C0.33 3.63 100% C0.50 3.80 48% C0.60 3.90 30% C0.70 4.00 20% C0.80 4.10 10% C0.90 4.20 8% C1.00 4.30 5% figure 8. product information on package table 11. package brand information brand key field description t temperature range pp package type z lead free option (optional) ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code vvvvvv.x n.n tppzccc b adsp-bf5xx a yyww country_of_origin caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the blackfin processor features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance de gradation or loss of functionality.
rev. b | page 26 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 timing specifications table 12 and table 13 describe the timing requirements for the adsp-bf534/adsp-bf536/adsp -bf537 processor clocks. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock and system clock. table 15 describes phase-locked l oop operating conditions. table 12. core clock requirements600 mhz speed grade 1 parameter min max unit f cclk core clock frequency (v ddint =1.2 v minimum) 600 mhz f cclk core clock frequency (v ddint =1.045 v minimum) 475 mhz f cclk core clock frequency (v ddint = 0.95 v minimum) 425 mhz f cclk core clock frequency (v ddint = 0.85 v minimum) 375 mhz f cclk core clock frequency (v ddint = 0.8 v ) 250 mhz 1 the speed grade of a given part is printed on the chips package as shown in figure 8 on page 25 and can also be seen on the specific pr oducts ordering guide. it stands for the maximum allowed cclk frequency at v ddint = 1.2 v and the maximum allowed vco frequency at any supply voltage. table 13. core clock requirements500 mhz speed grade 1 parameter min max unit f cclk core clock frequency (v ddint = 1.2 v minimum) 500 mhz f cclk core clock frequency (v ddint = 1.045 v minimum) 444 mhz f cclk core clock frequency (v ddint = 0.95 v minimum) 400 mhz f cclk core clock frequency (v ddint = 0.85 v minimum) 333 mhz f cclk core clock frequency (v ddint = 0.8 v ) 250 mhz 1 the speed grade of a given part is printed on the chips package as shown in figure 8 on page 25 and can also be seen on the specific pr oducts ordering guide. it stands for the maximum allowed cclk frequency at v ddint = 1.2 v and the maximum allowed vco frequency at any supply voltage. table 14. core clock requirements400 mhz speed grade 1 parameter min max unit f cclk core clock frequency (v ddint = 1.14 v minimum) 400 mhz f cclk core clock frequency (v ddint = 1.045 v minimum) 363 mhz f cclk core clock frequency (v ddint = 0.95 v minimum) 333 mhz f cclk core clock frequency (v ddint = 0.85 v minimum) 280 mhz f cclk core clock frequency (v ddint = 0.8 v ) 250 mhz 1 the speed grade of a given part is printed on the chips package as shown in figure 8 on page 25 and can also be seen on the specific pr oducts ordering guide. it stands for the maximum allowed cclk frequency at v ddint = 1.2 v and the maximum allowed vco frequency at any supply voltage. table 15. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency 50 speed grade 1 mhz 1 the speed grade of a given part is printed on the chips package as shown in figure 8 on page 25 and can also be seen on the specific pr oducts ordering guide. it stands for the maximum allowed cclk frequency at v ddint = 1.2 v and the maximum allowed vco frequency at any supply voltage.
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 27 of 68 | july 2006 table 16. system clock requirements parameter condition min max unit f sclk v ddext = 3.3 v, v ddint 1.14 v 133 mhz f sclk v ddext = 3.3 v, v ddint < 1.14 v 100 mhz f sclk v ddext = 2.5 v, v ddint 1.14 v 133 mhz f sclk v ddext = 2.5 v, v ddint < 1.14 v 100 mhz table 17. clock input and reset timing parameter min max unit timing requirement s t ckin clkin period 1 25.0 100.0 ns t ckinl clkin low pulse 2 10.0 ns t ckinh clkin high pulse 2 10.0 ns t bufdlay clkin to clkbuf delay 10 ns t wrst reset asserted pulse width low 3 11 t ckin ns 1 combinations of the clkin frequency and the p ll clock multiplier must not exceed the allowed f vco , f cclk , and f sclk settings discussed in table 12 through table 16 . since by default the pll is multiplying the clki n frequency by 10, 300 mhz and 400 mhz speed grade parts can not use the full clkin p eriod range. 2 applies to bypass mode and nonbypass mode. 3 applies after power-up sequence is complete . at power-up, the processor s internal phase-locked loop requires no more than 2000 clkin cycles while reset is asserted, assuming stable power supplies and clkin (not incl uding start-up time of external clock oscillator). figure 9. clock and reset timing reset clkin t ckinh t ckin t ckinl t wrst clkbuf t bufdlay t bufdlay
rev. b | page 28 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 asynchronous memory read cycle timing table 18. asynchronous memory read cycle timing parameter min max unit timing requirements t sdat data15C0 setup before clkout 2.1 ns t hdat data15C0 hold after clkout 0.8 ns t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic s t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, aoe , are . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 10. asynchronous memory read cycle timing t do t sdat clkout amsx abe1C0 t ho be, address read t hdat data15?0 aoe t do t sardy t hardy access extended 3cycles hold 1cycle are t hardy ardy addr19?1 setup 2cycles programmed read access 4cycles t ho t sardy
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 29 of 68 | july 2006 asynchronous memory write cycle timing table 19. asynchronous memory write cycle timing parameter min max unit timing requirements t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic s t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 1.0 ns t do output delay after clkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . 6.0 ns t ho output hold after clkout 1 0.8 ns figure 11. asynchronous memory write cycle timing t do t endat clkout amsx abe1?0 t ho write data t ddat data15?0 awe t sardy t hardy setup 2cycles programmed write access 2 cycles access extended 1cycle hold 1cycle ardy addr19?1 t ho t sardy t do be, address
rev. b | page 30 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 external port bus request and grant cycle timing table 20 and figure 12 describe external port bus request and bus grant operations. table 20. external port bus request and grant cycle timing parameter 1, 2 min max unit timing requirements t bs br asserted to clkout low setup 4.6 ns t bh clkout low to br deasserted hold time 0.0 ns switching characteristics t sd clkout low to amsx , address, and rd /wr disable 4.5 ns t se clkout low to amsx , address, and rd /wr enable 4.5 ns t dbg clkout high to bg asserted setup 3.6 ns t ebg clkout high to bg deasserted hold time 3.6 ns t dbh clkout high to bgh asserted setup 3.6 ns t ebh clkout high to bgh deasserted hold time 3.6 ns 1 these are preliminary timing parameters that ar e based on worst-case operating conditions. 2 the pad loads for these timing parameters are 20 pf. figure 12. external port bus request and grant cycle timing t bh addr19-1 amsx clkout t bs t sd t sd t sd t dbg t dbh t se t se t se t ebg t ebh bg awe bgh are br abe1-0
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 31 of 68 | july 2006 sdram interface timing table 21. sdram interface timing parameter min max unit timing requirement s t ssdat data setup before clkout 1.5 ns t hsdat data hold after clkout 0.8 ns switching characteristics t sclk clkout period 1 1 the t sclk value is the inverse of the f sclk specification discussed in table 16 . package type and reduced supply voltages affect the best-case value of 7.5 ns listed here. 7.5 ns t sclkh clkout width high 2.5 ns t sclkl clkout width low 2.5 ns t dcad command, addr, data delay after clkout 2 2 command pins include: sras , scas , swe , sdqm, sms , sa10, scke. 4.0 ns t hcad command, addr, data hold after clkout 2 1.0 ns t dsdat data disable after clkout 6.0 ns t ensdat data enable after clkout 1.0 ns figure 13. sdram interface timing t hcad t hcad t dsdat t dcad t ssdat t dcad t ensdat t hsdat t sclkl t sclkh t sclk clkout data (in) data (out) command addr (out) note: command = sras , scas , swe ,sdqm, sms ,sa10,scke.
rev. b | page 32 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 external dma request timing table 22 and figure 14 describe the external dma request operations. table 22. external dma request timing parameter min max unit timing requirements t dr dmarx asserted to clkout high setup 6.0 ns t dh clkout high to dmarx deasserted hold time 0.0 ns t dmaract dmarx active pulse width 1.0 t sclk ns t dmarinact dmarx inactive pulse width 1.75 t sclk ns figure 14. external dma request timing clkout t dr dmar0/1 (active low) t dh dmar0/1 (active high) t dmaract t dmarinact t dmarinact t dmaract
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 33 of 68 | july 2006 parallel peripheral interface timing table 23 and figure 15 on page 33 , figure 19 on page 37 , and figure 20 on page 38 describe parallel peripheral interface operations. table 23. parallel peripheral interface timing parameter min max unit timing requirements t pclkw ppi_clk width 1 6.0 ns t pclk ppi_clk period 1 15.0 ns timing requirementsgp input and frame capture modes t sfspe external frame sync setup before ppi_clk (nonsampling edge for rx, sampling edge for tx) 6.7 ns t hfspe external frame sync hold after ppi_clk 1.0 ns t sdrpe receive data setup before ppi_clk 3.5 ns t hdrpe receive data hold after ppi_clk 1.5 ns switching characteristicsgp ou tput and frame capture modes t dfspe internal frame sync delay after ppi_clk 8.0 ns t hofspe internal frame sync hold after ppi_clk 1.7 ns t ddtpe transmit data delay after ppi_clk 8.0 ns t hdtpe transmit data hold after ppi_clk 1.8 ns 1 ppi_clk frequency cannot exceed f sclk /2. figure 15. ppi gp rx mode with internal frame sync timing t s drpe t hdrpe pol s =0 pol s =0 polc = 0 pol s =1 pol s =1 frame s ync driving edge data s ampling edge data s ampling edge polc = 1 t df s pe t hof s pe ppi_clk ppi_clk ppi_f s 1 ppi_f s 2 ppi_data
rev. b | page 34 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 figure 16. ppi gp rx mode with external frame sync timing figure 17. ppi gp tx mode with internal frame sync timing pol s =0 pol s =0 polc = 0 pol s =1 pol s =1 data s ampling/ frame s ync s ampling edge data s ampling/ frame s ync s ampling edge polc = 1 t hf s pe t s f s pe ppi_data ppi_clk ppi_clk ppi_f s 1 ppi_f s 2 t s drpe t hdrpe t hdtpe t ddtpe pol s =0 pol s =0 polc = 0 pol s =1 pol s =1 data driving/ frame s ync driving edge data driving/ frame s ync driving edge polc = 1 t df s pe t hof s pe ppi_data ppi_clk ppi_clk ppi_f s 1 ppi_f s 2
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 35 of 68 | july 2006 figure 18. ppi gp tx mode with external frame sync timing t hdtpe t ddtpe pol s =0 pol s =0 polc = 0 pol s =1 pol s =1 data driving/ frame s ync s ampling edge data driving/ frame s ync s ampling edge polc = 1 t hf s pe t s f s pe ppi_data ppi_clk ppi_clk ppi_f s 1 ppi_f s 2
rev. b | page 36 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 serial ports table 24 through table 27 on page 37 and figure 19 on page 37 through figure 21 on page 39 describe serial port operations. table 24. serial portsexternal clock parameter min max unit timing requirements t sfse tfs/rfs setup before tsclk/rsclk 1 3.0 ns t hfse tfs/rfs hold after tsclk/rsclk 1 3.0 ns t sdre receive data setup before rsclk 1 3.0 ns t hdre receive data hold after rsclk 1 3.0 ns t sclkew tsclk/rsclk width 4.5 ns t sclke tsclk/rsclk period 15.0 ns switching characteristics t dfse tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 2 10.0 ns t hofse tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 2 0ns t ddte transmit data delay after tsclk 2 10.0 ns t hdte transmit data hold after tsclk 2 0ns 1 referenced to sample edge. 2 referenced to drive edge. table 25. serial portsinternal clock parameter min max unit timing requirements t sfsi tfs/rfs setup before tsclk/rsclk 1 8.0 ns t hfsi tfs/rfs hold after tsclk/rsclk 1 C1.5 ns t sdri receive data setup before rsclk 1 8.0 ns t hdri receive data hold after rsclk 1 C1.5 ns t sclkew tsclk/rsclk width 4.5 ns t sclke tsclk/rsclk period 15.0 ns switching characteristics t dfsi tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 2 3.0 ns t hofsi tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 2 ? 1.0 ns t ddti transmit data delay after tsclk 2 3.0 ns t hdti transmit data hold after tsclk 2 ? 1.0 ns t sclkiw tsclk/rsclk width 4.5 ns 1 referenced to sample edge. 2 referenced to drive edge. table 26. serial portsenable and three-state parameter min max unit switching characteristics t dtene data enable delay from external tsclk 1 0ns t ddtte data disable delay from external tsclk 1 10.0 ns t dteni data enable delay from internal tsclk 1 C2.0 ns t ddtti data disable delay from internal tsclk 1 3.0 ns 1 referenced to drive edge.
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 37 of 68 | july 2006 table 27. external late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 1, 2 10.0 ns t dtenlfs data enable from late fs or mce = 1, mfd = 0 1, 2 0ns 1 mce = 1, tfs enable and tfs valid follow t ddtenfs and t ddtlfs . 2 if external rfs/tfs setup to rsclk/tsclk > t sclke /2, then t ddte/i and t dtene/i apply, otherwise t ddtlfse and t dtenlfs apply. figure 19. serial ports dt dt t ddtte t ddtene t ddtti t ddteni drive edge drive edge drive edge drive edge tsclk/rsclk tsclk/rsclk tsclk (ext.) tfs (?late,? ext.) tsclk (int.) tfs (?late,? int.) t sdri rsclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive - internal clock t sdre data receive - external clock rsclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkew t hofse note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t ddti t hdti tsclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfsi t hofsi data transmit - internal clock t ddte t hdte tsclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkew t hofse data transmit - external clock note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge.
rev. b | page 38 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 figure 20. external late frame sync (frame sync setup < t sclke /2) t ddtlfse t sfse/i t hdte/i rsclk drive drive sample rfs dt 2nd bit 1st bit t dtenlfs t ddte/i t hofse/i t dtenlfs t sfse/i t hdte/i drive drive sample dt tsclk tfs 2nd bit 1st bit t ddtlfse t ddte/i t hofse/i external rfs with mce = 1, mfd = 0 late external tfs
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 39 of 68 | july 2006 figure 21. external late frame sync (frame sync setup > t sclke /2) dt rsclk rfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive dt tsclk tfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive late external tfs external rfs with mce = 1, mfd = 0
rev. b | page 40 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 serial peripheral interface portmaster timing table 28 and figure 22 describe spi port master operations. table 28. serial peripheral interface (spi) portmaster timing parameter min max unit timing requirements t sspidm data input valid to sck edge (data input setup) 7.5 ns t hspidm sck sampling edge to data input invalid C1.5 ns switching characteristics t sdscim spiselx low to first sck edge (x = 0 or x = 1) 2 t sclk C1.5 ns t spichm serial clock high period 2 t sclk C1.5 ns t spiclm serial clock low period 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk C1.5 ns t hdsm last sck edge to spiselx high (x = 0 or x = 1) 2 t sclk C1.5 ns t spitdm sequential transfer delay 2 t sclk C1.5 ns t ddspidm sck edge to data out valid (data out delay) 0 6 ns t hdspidm sck edge to data out invalid (data out hold) C1.0 +4.0 ns figure 22. serial peripheral interface (spi) portmaster timing t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) spiselx (output) sck (cpol = 0) (output) sck (cpol = 1) (output) t spichm t spiclm t spiclm t spiclk t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cpha = 1 cpha = 0 msb valid t sdscim t sspidm lsb valid
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 41 of 68 | july 2006 serial peripheral interface portslave timing table 29 and figure 23 describe spi port slave operations. table 29. serial peripheral interface (spi) portslave timing parameter min max unit timing requirements t spichs serial clock high period 2 t sclk C1.5 ns t spicls serial clock low period 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk C1.5 ns t hds last sck edge to spiss not asserted 2 t sclk C1.5 ns t spitds sequential transfer delay 2 t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2 t sclk C1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 ns t hspid sck sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 8 ns t dsdhi spiss deassertion to data high impedance 0 8 ns t ddspid sck edge to data out valid (data out delay) 0 10 ns t hdspid sck edge to data out invalid (data out hold) 0 10 ns figure 23. serial peripheral interface (spi) portslave timing t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t ddspid t hdspid miso (output) mosi (input) t sspid spiss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) t sdsci t spichs t spicls t spicls t spiclk t hds t spichs t sspid t hspid t dsdhi lsb valid msb msb valid t dsoe t ddspid miso (output) mosi (input) t sspid lsb valid lsb cpha = 1 cpha = 0 t spitds
rev. b | page 42 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing figure 24 describes the uart ports receive and transmit opera- tions. the maximum baud rate is sclk/16. as shown in figure 24 there is some latency between the generation of internal uart interrupts and the external data operations. these latencies are negligible at the data transmission rates for the uart. figure 24. uart portsrece ive and transmit timing uartx rx data(5?8) internal uart receive interrupt uart receive bit set by data stop; cleared by fifo read clkout (sample clock) uartx tx data(5?8) stop (1?2) internal uart transmit interrupt uart transmit bit set by program; cleared by write to transmit start stop transmit receive
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 43 of 68 | july 2006 general-purpose port timing table 30 and figure 25 describe general-purpose port operations. table 30. general-purpose port timing parameter min max unit timing requirement t wfi general-purpose port pin input pulse width t sclk + 1 ns switching characteristic t gpod general-purpose port pin output delay from clkout low 0 6 ns figure 25. general-purpose port timing gpp input gpp output clkout t gpod t wfi
rev. b | page 44 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 timer cycle timing table 31 and figure 26 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. table 31. timer cycle timing parameter min max unit timing characteristics t wl timer pulse width input low (measured in sclk cycles) 1 1 t sclk ns t wh timer pulse width input high (measured in sclk cycles) 1 1 t sclk ns t tis timer input setup time before clkout low 2 5ns t tih timer input hold time after clkout low 2 C2 ns switching characteristics t hto timer pulse width output (measured in sclk cycles) 1 t sclk (2 32 C1) t sclk ns t tod timer output update delay after clkout high 6 ns 1 the minimum pulse widths apply for tmrx sign als in width capture and external clock mode s. they also apply to the pf15 or ppi_c lk signals in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 26. timer cycle timing timer input timer output clkout t tis t tih t to d t wh, t wl t hto
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 45 of 68 | july 2006 timer clock timing table 32 and figure 27 describe timer clock timing. table 32. timer clock timing parameter min max unit switching characteristic t todp timer output update delay after ppiclk high 12 ns figure 27. timer clock timing timer output ppi clock t todp
rev. b | page 46 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 jtag test and emulation port timing table 33 and figure 28 describe jtag port operations. table 33. jtag port timing parameter min max unit timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 1 4ns t hsys system inputs hold after tck high 1 5ns t trstw trst pulse width 2 (measured in tck cycles) 4 tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system outputs delay after tck low 3 012ns 1 system inputs = data15C0, br , ardy, scl, sda, tfs0, tsclk0, rsclk0, rfs0, dr0pri, dr 0sec, pf15C0, pg15C0, ph15C0, mdio, tck, td1, tms, trst , reset , nmi , bmode2C0. 2 50 mhz maximum 3 system outputs = data15C0, addr19C1, abe1C0 , aoe , are , awe , ams3C0 , sras , scas , swe , scke, clkout, sa10, sms , scl, sda, tsclk0, tfs0, rfs0, rsclk0, dt0pri, dt0sec, pf15C0, pg15C0, ph15C0, rtx0, td0, emu , xtal, vrout. figure 28. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 47 of 68 | july 2006 10/100 ethernet mac controller timing table 34 through table 39 and figure 29 through figure 34 describe the 10/100 et hernet mac controlle r operations. this feature is only available on the adsp-bf536 and adsp-bf537 processors. for more information, see table 1 on page 3 . table 34. 10/100 ethernet mac controll er timing: mii receive signal parameter 1 min max unit t erxclkf erxclk frequency (f sclk = sclk frequency) none 25 mhz + 1% f sclk + 1% ns t erxclkw erxclk width (t erxclk = erxclk period) t erxclk 35% t erxclk 65% ns t erxclkis rx input valid to erxclk rising edge (data in setup) 7.5 ns t erxclkih erxclk rising edge to rx input invalid (data in hold) 7.5 ns 1 mii inputs synchronous to erxclk are erxd3C0, erxdv, and erxer. table 35. 10/100 ethernet mac controll er timing: mii transmit signal parameter 1 min max unit t etf etxclk frequency (f sclk = sclk frequency) none 25 mhz + 1% f sclk + 1% ns t etxclkw etxclk width (t etxclk = etxclk period) t etxclk 35% t etxclk 65% ns t etxclkov etxclk rising edge to tx output valid (data out valid) 20 ns t etxclkoh etxclk rising edge to tx output invalid (data out hold) 0 ns 1 mii outputs synchronous to etxclk are etxd3C0. table 36. 10/100 ethernet mac controll er timing: rmii receive signal parameter 1 min max unit t erefclkf ref_clk frequency (f sclk = sclk frequency) none 50 mhz + 1% 2 f sclk + 1% ns t erefclkw eref_clk width (t erefclk = erefclk period) t erefclk 35% t erefclk 65% ns t erefclkis rx input valid to rmii ref_clk rising edge (data in setup) 4 ns t erefclkih rmii ref_clk rising edge to rx input invalid (data in hold) 2 ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. table 37. 10/100 ethernet mac controller timing: rmii transmit signal parameter 1 min max unit t erefclkov rmii ref_clk rising edge to tx output valid (data out valid) 7.5 ns t erefclkoh rmii ref_clk rising edge to tx output invalid (data out hold) 2 ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0.
rev. b | page 48 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 table 38. 10/100 ethernet mac controller timing: mii/rmii asynchronous signal parameter 1, 2 min max unit t ecolh col pulse width high t etxclk 1.5 t erxclk 1.5 ns t ecoll col pulse width low t etxclk 1.5 t erxclk 1.5 ns t ecrsh crs pulse width high t etxclk 1.5 ns t ecrsl crs pulse width low t etxclk 1.5 ns 1 mii/rmii asynchronous signals are col, crs. th ese signals are applicable in both mii an d rmii modes. the asynchronous col input is synchronized se parately to both the etxclk and the erxclk, and must have a minimum pulse width high or low at least 1.5 times the period of the sl ower of the t wo clocks. 2 the asynchronous crs input is synchronized to the etxclk, and mus t have a minimum pulse width high or low at least 1.5 times th e period of etxclk. table 39. 10/100 ethernet mac controller timing: mii station management parameter 1 min max unit t mdios mdio input valid to mdc rising edge (setup) 10 ns t mdcih mdc rising edge to mdio input invalid (hold) 10 ns t mdcov mdc falling edge to mdio output valid 25 ns t mdcoh mdc falling edge to mdio output invalid (hold) C1 ns 1 mdc/mdio is a 2-wire serial bidirectional port for controlling one or more external phys. mdc is an output clock whose minimum period is programmable as a multiple of the system clock sclk. mdio is a bidirectional data line. figure 29. 10/100 ethernet mac controller timing: mii receive signal figure 30. 10/100 ethernet mac controller timing: mii transmit signal erxd3-0 erxdv erxer erxclk t erxclk t erxclkis t erxclkih t erxclkw etxd3-0 etxen mii txclk t etxclk t etxclkoh t etxclkov t etxclkw
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 49 of 68 | july 2006 figure 31. 10/100 ethernet mac controller timing: rmii receive signal figure 32. 10/100 ethernet mac controller timing: rmii transmit signal figure 33. 10/100 ethernet mac controller timing: asynchronous signal figure 34. 10/100 ethernet mac contro ller timing: mii station management erxd1-0 erxdv erxer erxclk t refclk t erxclkis t erxclkih t refclkw etxd1-0 etxen rmii ref_clk t refclk t erefclkoh t erefclkov mii crs, col t ecrsh t ecrsl t ecolh t ecoll mdio (output) mdc (output) t mdcoh t mdios t mdcih mdio (input) t mdcov
rev. b | page 50 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 output drive currents figure 35 through figure 46 show typical current-voltage char- acteristics for the output drivers of the processors. the curves represent the current drive capability of the output drivers as a function of output voltage. see table 9 on page 19 for informa- tion about which driver type co rresponds to a particular pin. figure 35. drive current a (low v ddext ) figure 36. drive current a (high v ddext ) 0 s o u r c e c u r r e n t ( m a ) source vol tage (v) 0 0.5 1.0 1.5 2.0 2.5 3. 0 10 0 60 40 - 80 - 60 - 40 - 20 12 0 20 80 - 10 0 v ddext =2.25v@95c v ddext =2.50v@25c v ddext =2.75v@ - 40 c v oh v ol 0 s o u r c e c u r r e n t ( m a ) source v oltage ( v ) 0 0.51.01.52.02.53.03.5 15 0 10 0 50 - 15 0 - 10 0 - 50 v ol v oh 4.0 v ddext =3.0v@95c v ddext =3.3v@25c v ddext =3.6v@ - 40 c figure 37. drive current b (low v ddext ) figure 38. drive current b (high v ddext ) 0 s o u r c e c u r r e n t ( m a ) s ource voltage (v ) 0 0.5 1. 0 1.5 2 .0 2. 5 3.0 15 0 10 0 - 15 0 v ol v oh - 10 0 - 50 50 v ddext =2.25v@95c v dd e xt =2.50v@25c v ddext =2.75v @ - 40 c 0 s o u r c e c u r r e n t ( m a ) source voltage (v) 0 0.51.01.52.02.53.03.5 15 0 10 0 50 - 200 - 150 v ol v oh 4.0 - 100 - 50 20 0 v dd e xt =3.0v@95c v dd e xt =3.3v@25c v ddext =3.6v@ - 40 c
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 51 of 68 | july 2006 figure 39. drive current c (low v ddext ) figure 40. drive current c (high v ddext ) figure 41. drive current d (low v ddext ) 0 s o u r c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1. 0 1.5 2 .0 2. 5 3.0 80 60 - 60 v ol v oh - 40 - 20 40 20 v d d ext =2.25v@95c v d d ext =2.50v@25c v ddext =2.75v@ - 40c 0 s o u r c e c u r r e n t ( m a ) source voltage (v) 0 0.51.01.52.02.53.03.5 80 60 40 - 80 - 60 v ol v oh 4.0 - 40 - 20 10 0 20 v ddext =3.0v@95c v ddext =3.3v@25c v dd e xt =3.6v@ - 40c 0 s o u r c e c u r r e n t ( m a ) source voltage (v) 0 0.51.01.52.02.53.0 80 60 40 - 80 - 60 v ol v oh - 40 - 20 10 0 20 v ddext =2.25v@ 95c v ddext =2.50v@ 25c v ddext =2.75v@ - 40c figure 42. drive current d (high v ddext ) figure 43. drive current e (low v ddext ) figure 44. drive current e (high v ddext ) 0 s o u r c e c u r r e n t ( m a ) source voltage (v) 0 0.51.01.52.02.53.03.5 10 0 50 - 150 v ol v oh 4.0 - 100 - 50 15 0 v ddext =3.0v@95c v ddext =3.3v@25c v dd e xt =3.6v@ - 40 c 0 s o u r c e c u r r e n t ( m a ) source vol tage (v) 0 0.5 1.0 1.5 2.0 2.5 3. 0 40 20 10 - 40 - 30 v ol v oh v ddext =2.25v@95c v ddext =2.50v@25c v ddext =2.75v@ - 40c - 20 - 10 50 30 - 50 0 s o u r c e c u r r e n t ( m a ) source voltage (v) 0 0.51.01.52.02.53.03.5 80 60 40 - 80 - 60 v ol v oh v ddext =3.0v@95c v ddext =3.3v@25c v dd e xt =3.6v@ - 40 c 4.0 - 40 - 20 20
rev. b | page 52 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 figure 45. drive current f (low v ddext ) figure 46. drive current f (high v ddext ) - 40 s o u r c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1 .5 2.0 2.5 3.0 - 60 0 - 10 v ol - 20 - 30 - 50 v dd e xt =2.25v@95c v dd e xt =2.50v@25c v ddext =2.75v@ - 40c - 40 s o u r c e c u r r e n t ( m a ) s ource voltage (v ) 0 0.51.01.52.02.53.03.5 0 - 10 - 20 - 80 - 70 v ol 4.0 - 60 - 50 - 30 v ddext =3.0v@ 95c v ddext =3.3v@ 25c v ddext =3.6v@ - 40c
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 53 of 68 | july 2006 power dissipation total power dissipation has two components: one due to inter- nal circuitry (p int ) and one due to the switching of external output drivers (p ext ). table 40 shows the power dissipation for internal circuitry (v ddint ). many operating conditions can affect power dissipation. system designers should refer to ee-297: estimating power for the adsp-bf534/bf536/bf537 blackfin processors . this document will provide detailed information for optimizing your design for lowest power. the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? the output voltage swing (v ddext ). ? the output capacitance (c 0 ) individual pins have to load. ? the maximum frequency (f 0 ) at which individual pins switch. furthermore, because i/o activity is usually not constant over time, the external component of power dissipation is not a con- stant value. its peak value is best estimated by identifying representative phases with the highest i/o activity and analyz- ing output switching pin by pin. the following formula calculates the average power for an analyzed period by accumu- lating the power of all output pins. the frequency f includ es driving the load high and then back low. for example: data15C0 pins can drive high and low at a maximum rate of 1 (2 t sclk ) while in sdram burst mode. a typical power consum ption can now be calculated for these conditions by adding a typical internal power dissipation: note that the conditions causing a worst-case p ext differ from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). note, as well, that it is uncommon for an applica- tion to have 100% or even 50% of the outputs switching simultaneously. table 40. internal power dissipation test conditions 1 parameter f cclk = 50 mhz v ddint = 0.8 v f cclk = 400 mhz v ddint =1.0 v f cclk = 400 mhz v ddint =1.2 v unit i ddtyp 2 26 130 160 ma i ddsleep 3, 4 16 30 37 ma i dddeepsleep 3 14 25 31 ma i ddhibernate 4 50 50 50 a i ddrtc 5 30 30 30 a parameter f cclk = 250 mhz v ddint =0.8 v f cclk = 500 mhz v ddint =1.2 v unit i ddtyp 2 65 190 ma i ddsleep 3, 4 16 37 ma i dddeepsleep 3 14 31 ma i ddhibernate 4 50 50 a i ddrtc 5 30 30 a parameter f cclk = 600 mhz v ddint =1.2 v unit i ddtyp 2 220 ma i ddsleep 3, 4 37 ma i dddeepsleep 3 31 ma i ddhibernate 4 50 a i ddrtc 5 30 a 1 i dd data is specified for typical pr ocess parameters. all data at 25 c. 2 processor executing 75% dual mac, 25% add with moderate data bus activity. 3 see the adsp-bf537 blackfin processor hardware reference manual for definitions of sleep and deep sleep operating modes. 4 i ddhibernate is measured @ v ddext = 3.65 v with the core voltage regulator off (v ddint =0v). 5 measured at v ddrtc = 3.3 v at 25 c. p ext v ddext 2 c 0 f 0 ? = p total p ext i dd v ddint () + =
rev. b | page 54 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 test conditions all timing parameters appearing in this data sheet were measured under the conditions described in this section. output enable time output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the output enable/disable diagram ( figure 47 ). the time t ena_measured is the interval from wh en the reference signal switches to when the output voltage reaches 2.0 v (output high) or 1.0 v (output low). time t trip is the interval from when the output starts driving to when the output reaches the 1.0 v or 2.0 v trip voltage. time t ena is calculated as shown in the equation: if multiple pins (such as the da ta bus) are enab led, the measure- ment value is that of the first pin to start driving. output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the equation: the output disable time t dis is the difference between t dis_measured and t decay as shown in figure 47 . the time t dis_measured is the interval from when the reference signal switches to when the output voltage decays v from the mea- sured output-high or output -low voltage. the time t decay is calculated with test loads c l and i l , and with v equal to 0.5 v. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the processors output voltage and the input threshold for the device requiring the hold time. a typical v is 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three- state current (per data line). the hold time is t decay plus the minimum disable time (for example, t dsdat for an sdram write cycle). t ena t ena_measured t trip ? = t decay c l v () i l ? = figure 47. output enable/disable figure 48. equivalent device loading for ac measurements (includes all fixtures) figure 49. voltage reference levels for ac measurements (except output enable/disable) reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured) v ol (measured) high impedance state output stops driving t ena t decay t ena _measured t trip v trip (low) v load 30pf to output pin 50 input or output v meas v meas
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 55 of 68 | july 2006 capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 48 ). figure 50 through figure 59 on page 57 show how output rise time varies with capacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. figure 50. typical output delay or hold for driver a at v ddext min figure 51. typical output delay or hold for driver a at v ddext max abe0 (1 33 mhz driver), v ddext (min) = 2.25v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% t0 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time abe0 (1 33 mhz driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time figure 52. typical output delay or hold for driver b at v ddext min figure 53. typical output delay or hold for driver b at v ddext max clkout (clkout driver), v ddext (min) = 2.25v, temperature = 8 5 c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time clkout (clkout driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 fall time
rev. b | page 56 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 figure 54. typical output delay or hold for driver c at v ddext min figure 55. typical output dela y or hold for driver c at v ddext max pf9 ( 33 mhz driver), v ddext (min) = 2.25v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 25 3 0 20 15 10 5 0 0 50 100 150 200 250 fall time pf9 ( 33 mhz driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 20 1 8 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time figure 56. typical output delay or hold for driver d at v ddext min figure 57. typical output delay or hold for driver d at v ddext max s ck (66 mhz driver), v ddext (min) = 2.25v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 1 8 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time s ck (66 mhz driver), v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 57 of 68 | july 2006 figure 58. typical output delay or hold for driver e at v ddext min figure 59. typical output dela y or hold for driver e at v ddext max ph0 v ddext (min) = 2.25v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 3 6 3 2 2 8 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time ph0 v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 3 6 3 2 2 8 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time figure 60. typical output dela y or hold for driver f at v ddext min figure 61. typical output delay or hold for driver f at v ddext max ph0 v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 3 6 3 2 2 8 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time ph0 v ddext (max) = 3 .65v, temperature = 8 5c load capacitance (pf) ri s e time ri s e and fall time n s (10% to 90%) 3 6 3 2 2 8 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time
rev. b | page 58 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 thermal characteristics to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature ( c) t case = case temperature ( c) measured by customer at top center of package. jt = from table 41 p d = power dissipation (see power dissipation on page 53 for the method to calculate p d ) values of ja are provided for packag e comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature ( c) values of jc are provided for package comparison and printed circuit board design considerations when an external heat sink is required. values of jb are provided for packag e comparison and printed circuit board design considerations. in table 41 through table 43 , airflow measurements comply with jedec standard s jesd51-2 and jesd51-6, and the junc- tion-to-board measurement comp lies with jesd51-8. test board and thermal via design comply with jedec standards jesd51-9 (bga). the junction-t o-case measurement complies with mil-std-883 (method 1012. 1). all measurements use a 2s2p jedec test board. industrial applications using the 208-ball bga package require thermal vias, to an embedded grou nd plane, in the pcb. refer to jedec standard jesd51-9 for pr inted circuit board thermal ball land and thermal vi a design information. table 41. thermal characteristics (182-ball bga) parameter condition typical unit ja 0 linear m/s air flow 32.80 c/w jma 1 linear m/s air flow 29.30 c/w jma 2 linear m/s air flow 28.00 c/w jb 20.10 c/w jc 7.92 c/w jt 0 linear m/s air flow 0.19 c/w jt 1 linear m/s air flow 0.35 c/w jt 2 linear m/s air flow 0.45 c/w t j t case jt p d () + = t j t a ja p d () + = table 42. thermal characteristics (208-ball bga without thermal vias in pcb) parameter condition typical unit ja 0 linear m/s air flow 23.30 c/w jma 1 linear m/s air flow 20.20 c/w jma 2 linear m/s air flow 19.20 c/w jb 13.05 c/w jc 6.92 c/w jt 0 linear m/s air flow 0.18 c/w jt 1 linear m/s air flow 0.27 c/w jt 2 linear m/s air flow 0.32 c/w table 43. thermal characteristics (208-ball bga with thermal vias in pcb) parameter condition typical unit ja 0 linear m/s air flow 22.60 c/w jma 1 linear m/s air flow 19.40 c/w jma 2 linear m/s air flow 18.40 c/w jb 13.20 c/w jc 6.85 c/w jt 0 linear m/s air flow 0.16 c/w jt 1 linear m/s air flow 0.27 c/w jt 2 linear m/s air flow 0.32 c/w
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 59 of 68 | july 2006 182-ball mini-bga pinout table 44 lists the mini-bga pino ut by signal mnemonic. table 45 on page 60 lists the mini-bga pinout by ball number. table 44. 182-ball mini-bga ball assignment (alphabetically by signal mnemonic) mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. abe0 h13 clkout b14 gnd l6 pg8 e3 sras d13 abe1 h12 data0 m9 gnd l8 pg9 e4 swe d12 addr1 j14 data1 n9 gnd l10 ph0 c2 tck p2 addr10 m13 data10 n6 gnd m4 ph1 c3 tdi m3 addr11 m14 data11 p6 gnd m10 ph10 b6 tdo n3 addr12 n14 data12 m5 gnd p14 ph11 a2 tms n2 addr13 n13 data13 n5 nmi b10 ph12 a3 trst n1 addr14 n12 data14 p5 pf0 m1 ph13 a4 vddext a1 addr15 m11 data15 p4 pf1 l1 ph14 a5 vddext c12 addr16 n11 data2 p9 pf10 j2 ph15 a6 vddext e6 addr17 p13 data3 m8 pf11 j3 ph2 c4 vddext e11 addr18 p12 data4 n8 pf12 h1 ph3 c5 vddext f4 addr19 p11 data5 p8 pf13 h2 ph4 c6 vddext f12 addr2 k14 data6 m7 pf14 h3 ph5 b1 vddext h5 addr3 l14 data7 n7 pf15 h4 ph6 b2 vddext h10 addr4 j13 data8 p7 pf2 l2 ph7 b3 vddext j11 addr5 k13 data9 m6 pf3 l3 ph8 b4 vddext j12 addr6 l13 emu m2 pf4 l4 ph9 b5 vddext k7 addr7 k12 gnd a10 pf5 k1 pj0 c7 vddext k9 addr8 l12 gnd a14 pf6 k2 pj1 b7 vddext l7 addr9 m12 gnd d4 pf7 k3 pj10 d10 vddext l9 ams0 e14 gnd e7 pf8 k4 pj11 d11 vddext l11 ams1 f14 gnd e9 pf9 j1 pj2 b11 vddext p1 ams2 f13 gnd f5 pg0 g1 pj3 c11 vddint e5 ams3 g12 gnd f6 pg1 g2 pj4 d7 vddint e8 aoe g13 gnd f10 pg10 d1 pj5 d8 vddint e10 ardy e13 gnd f11 pg11 d2 pj6 c8 vddint g10 are g14 gnd g4 pg12 d3 pj7 b8 vddint k5 awe h14 gnd g5 pg13 d5 pj8 d9 vddint k8 bg p10 gnd g11 pg14 d6 pj9 c9 vddint k10 bgh n10 gnd h11 pg15 c1 reset c10 vddrtc b9 bmode0 n4 gnd j4 pg2 g3 rtxo a8 vrout0 a13 bmode1 p3 gnd j5 pg3 f1 rtxi a9 vrout1 b12 bmode2 l5 gnd j9 pg4 f2 sa10 e12 xtal a11 br d14 gnd j10 pg5 f3 scas c14 clkbuf a7 gnd k6 pg6 e1 scke b13 clkin a12 gnd k11 pg7 e2 sms c13
rev. b | page 60 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 table 45. 182-ball mini-bga ball assign ment (numerically by ball number) ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic a1 vddext c10 reset f5 gnd j14 addr1 m9 data0 a2 ph11 c11 pj3 f6 gnd k1 pf5 m10 gnd a3 ph12 c12 vddext f10 gnd k2 pf6 m11 addr15 a4 ph13 c13 sms f11 gnd k3 pf7 m12 addr9 a5 ph14 c14 scas f12 vddext k4 pf8 m13 addr10 a6 ph15 d1 pg10 f13 ams2 k5 vddint m14 addr11 a7 clkbuf d2 pg11 f14 ams1 k6 gnd n1 trst a8 rtxo d3 pg12 g1 pg0 k7 vddext n2 tms a9 rtxi d4 gnd g2 pg1 k8 vddint n3 tdo a10 gnd d5 pg13 g3 pg2 k9 vddext n4 bmode0 a11 xtal d6 pg14 g4 gnd k10 vddint n5 data13 a12 clkin d7 pj4 g5 gnd k11 gnd n6 data10 a13 vrout0 d8 pj5 g10 vddint k12 addr7 n7 data7 a14 gnd d9 pj8 g11 gnd k13 addr5 n8 data4 b1 ph5 d10 pj10 g12 ams3 k14 addr2 n9 data1 b2 ph6 d11 pj11 g13 aoe l1 pf1 n10 bgh b3 ph7 d12 swe g14 are l2 pf2 n11 addr16 b4 ph8 d13 sras h1 pf12 l3 pf3 n12 addr14 b5 ph9 d14 br h2 pf13 l4 pf4 n13 addr13 b6 ph10 e1 pg6 h3 pf14 l5 bmode2 n14 addr12 b7 pj1 e2 pg7 h4 pf15 l6 gnd p1 vddext b8 pj7 e3 pg8 h5 vddext l7 vddext p2 tck b9 vddrtc e4 pg9 h10 vddext l8 gnd p3 bmode1 b10 nmi e5 vddint h11 gnd l9 vddext p4 data15 b11 pj2 e6 vddext h12 abe1 l10 gnd p5 data14 b12 vrout1 e7 gnd h13 abe0 l11 vddext p6 data11 b13 scke e8 vddint h14 awe l12 addr8 p7 data8 b14 clkout e9 gnd j1 pf9 l13 addr6 p8 data5 c1 pg15 e10 vddint j2 pf10 l14 addr3 p9 data2 c2 ph0 e11 vddext j3 pf11 m1 pf0 p10 bg c3 ph1 e12 sa10 j4 gnd m2 emu p11 addr19 c4 ph2 e13 ardy j5 gnd m3 tdi p12 addr18 c5 ph3 e14 ams0 j9 gnd m4 gnd p13 addr17 c6 ph4 f1 pg3 j10 gnd m5 data12 p14 gnd c7 pj0 f2 pg4 j11 vddext m6 data9 c8 pj6 f3 pg5 j12 vddext m7 data6 c9 pj9 f4 vddext j13 addr4 m8 data3
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 61 of 68 | july 2006 figure 63 shows the top view of the mini-bga ball configura- tion. figure 62 shows the bottom view of the mini-bga ball configuration. figure 62. 182-ball mini-bga configuration (top view) a b c d e f g h j k l m n p 1234567891011121314 v ddint v ddext gnd i/o key: v rout v ddrtc figure 63. 182-ball mini-bga configuration (bottom view) a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ddint v ddext gnd i/o key: v rout v ddrtc
rev. b | page 62 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 208-ball sparse mini-bga pinout table 46 lists the sparse mini-bga pinout by signal mnemonic. table 47 on page 63 lists the sparse mini -bga pinout by ball number. table 46. 208-ball sparse mini-bga ball assign ment (alphabetically by signal mnemonic) mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. abe0 p19 data12 y4 gnd m13 pg6 e2 tdi v1 abe1 p20 data13 w4 gnd n9 pg7 d1 tdo y2 addr1 r19 data14 y3 gnd n10 pg8 d2 tms u2 addr10 w18 data15 w3 gnd n11 pg9 c1 trst u1 addr11 y18 data2 y9 gnd n12 ph0 b4 vddext g7 addr12 w17 data3 w9 gnd n13 ph1 a5 vddext g8 addr13 y17 data4 y8 gnd p11 ph10 b9 vddext g9 addr14 w16 data5 w8 gnd v2 ph11 a10 vddext g10 addr15 y16 data6 y7 gnd w2 ph12 b10 vddext h7 addr16 w15 data7 w7 gnd w19 ph13 a11 vddext h8 addr17 y15 data8 y6 gnd y1 ph14 b11 vddext j7 addr18 w14 data9 w6 gnd y13 ph15 a12 vddext j8 addr19 y14 emu t1 gnd y20 ph2 b5 vddext k7 addr2 t20 gnd a1 nmi c20 ph3 a6 vddext k8 addr3 t19 gnd a13 pf0 t2 ph4 b6 vddext l7 addr4 u20 gnd a20 pf1 r1 ph5 a7 vddext l8 addr5 u19 gnd b2 pf10 l2 ph6 b7 vddext m7 addr6 v20 gnd g11 pf11 k1 ph7 a8 vddext m8 addr7 v19 gnd h9 pf12 k2 ph8 b8 vddext n7 addr8 w20 gnd h10 pf13 j1 ph9 a9 vddext n8 addr9 y19 gnd h11 pf14 j2 pj0 b12 vddext p7 ams0 m20 gnd h12 pf15 h1 pj1 b13 vddext p8 ams1 m19 gnd h13 pf2 r2 pj10 b19 vddext p9 ams2 g20 gnd j9 pf3 p1 pj11 c19 vddext p10 ams3 g19 gnd j10 pf4 p2 pj2 d19 vddint g12 aoe n20 gnd j11 pf5 n1 pj3 e19 vddint g13 ardy j19 gnd j12 pf6 n2 pj4 b18 vddint g14 are n19 gnd j13 pf7 m1 pj5 a19 vddint h14 awe r20 gnd k9 pf8 m2 pj6 b15 vddint j14 bg y11gndk10pf9l1 pj7 b16vddintk14 bgh y12gndk11pg0h2 pj8 b17vddintl14 bmode0 w13 gnd k12 pg1 g1 pj9 b20 vddint m14 bmode1 w12 gnd k13 pg10 c2 reset d20 vddint n14 bmode2 w11 gnd l9 pg11 b1 rtxo a15 vddint p12 br f19 gnd l10 pg12 a2 rtxi a14 vddint p13 clkbuf b14 gnd l11 pg13 a3 sa10 l20 vddint p14 clkin a18 gnd l12 pg14 b3 scas k20 vddrtc a16 clkout h19 gnd l13 pg15 a4 scke h20 vrout0 e20 data0 y10 gnd m9 pg2 g2 sms j20 vrout1 f20 data1 w10 gnd m10 pg3 f1 sras k19 xtal a17 data10 y5 gnd m11 pg4 f2 swe l19 data11 w5 gnd m12 pg5 e1 tck w1
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 63 of 68 | july 2006 table 47 lists the sparse mini-bga pinout by ball number. table 46 on page 62 lists the sparse mini-b ga pinout by signal mnemonic. table 47. 208-ball sparse mini-bga ball as signment (numerically by ball number) ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic ball no. mnemonic a1 gnd c19 pj11 j9 gnd m19 ams1 w1 tck a2 pg12 c20 nmi j10 gnd m20 ams0 w2 gnd a3 pg13 d1 pg7 j11 gnd n1 pf5 w3 data15 a4 pg15 d2 pg8 j12 gnd n2 pf6 w4 data13 a5 ph1 d19 pj2 j13 gnd n7 vddext w5 data11 a6 ph3 d20 reset j14 vddint n8 vddext w6 data9 a7 ph5 e1 pg5 j19 ardy n9 gnd w7 data7 a8 ph7 e2 pg6 j20 sms n10 gnd w8 data5 a9 ph9 e19 pj3 k1 pf11 n11 gnd w9 data3 a10 ph11 e20 vrout0 k2 pf12 n12 gnd w10 data1 a11 ph13 f1 pg3 k7 vddext n13 gnd w11 bmode2 a12 ph15 f2 pg4 k8 vddext n14 vddint w12 bmode1 a13 gnd f19 br k9 gnd n19 are w13 bmode0 a14 rtxi f20 vrout1 k10 gnd n20 aoe w14 addr18 a15 rtxo g1 pg1 k11 gnd p1 pf3 w15 addr16 a16 vddrtc g2 pg2 k12 gnd p2 pf4 w16 addr14 a17 xtal g7 vddext k13 gnd p7 vddext w17 addr12 a18 clkin g8 vddext k14 vddint p8 vddext w18 addr10 a19 pj5 g9 vddext k19 sras p9 vddext w19 gnd a20 gnd g10 vddext k20 scas p10 vddext w20 addr8 b1 pg11 g11 gnd l1 pf9 p11 gnd y1 gnd b2 gnd g12 vddint l2 pf10 p12 vddint y2 tdo b3 pg14 g13 vddint l7 vddext p13 vddint y3 data14 b4 ph0 g14 vddint l8 vddext p14 vddint y4 data12 b5 ph2 g19 ams3 l9 gnd p19 abe0 y5 data10 b6 ph4 g20 ams2 l10 gnd p20 abe1 y6 data8 b7 ph6 h1 pf15 l11 gnd r1 pf1 y7 data6 b8 ph8 h2 pg0 l12 gnd r2 pf2 y8 data4 b9 ph10 h7 vddext l13 gnd r19 addr1 y9 data2 b10 ph12 h8 vddext l14 vddint r20 awe y10 data0 b11 ph14 h9 gnd l19 swe t1 emu y11 bg b12 pj0 h10 gnd l20 sa10 t2 pf0 y12 bgh b13 pj1 h11 gnd m1 pf7 t19 addr3 y13 gnd b14 clkbuf h12 gnd m2 pf8 t20 addr2 y14 addr19 b15 pj6 h13 gnd m7 vddext u1 trst y15 addr17 b16 pj7 h14 vddint m8 vddext u2 tms y16 addr15 b17 pj8 h19 clkout m9 gnd u19 addr5 y17 addr13 b18 pj4 h20 scke m10 gnd u20 addr4 y18 addr11 b19pj10j1 pf13m11gndv1 tdi y19addr9 b20 pj9 j2 pf14 m12 gnd v2 gnd y20 gnd c1 pg9 j7 vddext m13 gnd v19 addr7 c2 pg10 j8 vddext m14 vddint v20 addr6
rev. b | page 64 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 figure 64 shows the top view of the sparse mini-bga ball con- figuration. figure 65 shows the bottom view of the sparse mini- bga ball configuration. figure 64. 208-ball mini-bga configuration (top view) a b c d e f g h j k l m n p 1234567891011121314 1617181920 15 v ddint v ddext gnd i/o key: v rout v ddrtc r t u v w y figure 65. 208-ball mini-bga configuration (bottom view) a b c d e f g h j k l m n p 20 19 18 17 16 15 14 13 12 11 10 9 8 7 5 4 3 2 1 6 v ddint v ddext gnd i/o key: v rout v ddrtc r t u v w y
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 65 of 68 | july 2006 outline dimensions dimensions in figure 66 and figure 67 are shown in millimeters. figure 66. 182-ball mini-bga (bc-182) figure 67. 208-ball sparse mini-bga (bc-208-2) 0.80 bsc typ detail a detail a 0.50 0.45 0.40 1.31 1.21 1.10 10.40 bsc sq a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 95 4 a 1corner index area top view bottom view 1.70 1.56 1.35 12.00 bsc sq (ball diameter) seating plane 0.35 nom 0.25 min 0.12 coplanarity pin a1 indicator location notes: 1. dimensions are in millimeters. 2. compliant to jedec standard mo-205-ae, except for ball diameter. 3. center dimensions are nominal. 4. the actual position of the ball grid is within 0.15 of its ideal position relative to the package edges. 0.80 bsc typ a b c d e f g h j k l m n p r t u v w y 15 14 17 16 19 18 20 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 15.20 bsc sq a 1corner index area 0.12 coplanarity detail a 0.50 0.45 0.40 (ball diameter) 0.35 nom 0.25 min top view pin a1 indicator location detail a 17.00 bsc sq seating plane 1.70 1.56 1.35 1.31 1.21 1.10 notes: 1. dimensions are in millimeters. 2. compliant to jedec standard mo-205-am, except for ball diameter. 3. center dimensions are nominal. 4. the actual position of the ball grid is within 0.15 of its ideal position relative to the package edges.
rev. b | page 66 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 surface mount design the following table is provided as an aide to pcb design. for industry-standard desi gn recommendations, refer to ipc-7351, generic requirements for surfac e mount design and land pat- tern standard . ordering guide package ball attach type solder mask opening ball pad size 182-ball mini-bga (bc-182) solder mask defined 0.40 mm diameter 0.55 mm diameter 208-ball sparse mini-bga (bc-208-2) solder mask defined 0.40 mm diameter 0.55 mm diameter model temperature range 1 1 referenced temperature is ambient temperature. speed grade (max) operating voltage (nominal) package description package option ADSP-BF534BBC-4A C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf534bbcz-4a 2 2 z = pb-free part. C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf534bbc-5a C40 c to +85 c 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf534bbcz-5a 2 C40 c to +85 c 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf534bbcz-4b 2 C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf534bbcz-5b 2 C40 c to +85 c 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf534ybcz-4b 2 C40 c to +105 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf534wybcz-4b 2, 3 3 the w in the model number signifies that a ve rsion of this product is available for us e in automotive appl ications. co ntact you r local adi sales office for complete ordering information. C40 c to +105 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf534wbbcz-4a 2, 3 C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf534wbbcz-4b 2, 3 C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf534wbbcz-5b 2, 3 C40 c to +85 c 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf536bbc-3a C40 c to +85 c 300 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf536bbcz-3a 2 C40 c to +85 c 300 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf536bbc-4a C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf536bbcz-4a 2 C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf536bbcz-3b 2 C40 c to +85 c 300 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf536bbcz-4b 2 C40 c to +85 c 400 mhz 1.2 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf537bbc-5a C40 c to +85 c 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf537bbcz-5a 2 C40 c to +85 c 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf537kbc-6a 0 c to 70 c 600 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf537kbcz-6a 2 0 c to 70 c 600 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 182-ball mini-bga bc-182 adsp-bf537bbcz-5b 2 C40 c to +85 c 500 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2 adsp-bf537kbcz-6b 2 0 c to 70 c 600 mhz 1.26 v internal, 2.5 v or 3.3 v i/o 208-ball sparse mini-bga bc-208-2
adsp-bf534/adsp-bf536/adsp-bf537 rev. b | page 67 of 68 | july 2006
rev. b | page 68 of 68 | july 2006 adsp-bf534/adsp-bf536/adsp-bf537 ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners.

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